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Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00005 */
6
Dimitris Papastamose08005a2017-10-12 13:02:29 +01007#include <amu.h>
Achin Gupta27b895e2014-05-04 18:38:28 +01008#include <arch.h>
Achin Gupta7aea9082014-02-01 07:51:28 +00009#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010010#include <assert.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000011#include <bl_common.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010012#include <context.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000013#include <context_mgmt.h>
Achin Gupta191e86e2014-05-09 10:03:15 +010014#include <interrupt_mgmt.h>
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +010015#include <mpam.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010016#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010017#include <platform_def.h>
Dimitris Papastamosa7921b92017-10-13 15:27:58 +010018#include <pubsub_events.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000019#include <smccc_helpers.h>
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +010020#include <spe.h>
Andrew Thoelke4e126072014-06-04 21:10:52 +010021#include <string.h>
David Cunadoce88eee2017-10-20 11:30:57 +010022#include <sve.h>
Douglas Raillarda8954fc2017-01-26 15:54:44 +000023#include <utils.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000024
Achin Gupta7aea9082014-02-01 07:51:28 +000025
26/*******************************************************************************
27 * Context management library initialisation routine. This library is used by
28 * runtime services to share pointers to 'cpu_context' structures for the secure
29 * and non-secure states. Management of the structures and their associated
30 * memory is not done by the context management library e.g. the PSCI service
31 * manages the cpu context used for entry from and exit to the non-secure state.
32 * The Secure payload dispatcher service manages the context(s) corresponding to
33 * the secure state. It also uses this library to get access to the non-secure
34 * state cpu context pointers.
35 * Lastly, this library provides the api to make SP_EL3 point to the cpu context
36 * which will used for programming an entry into a lower EL. The same context
37 * will used to save state upon exception entry from that EL.
38 ******************************************************************************/
Juan Castillo2d552402014-06-13 17:05:10 +010039void cm_init(void)
Achin Gupta7aea9082014-02-01 07:51:28 +000040{
41 /*
42 * The context management library has only global data to intialize, but
43 * that will be done when the BSS is zeroed out
44 */
45}
46
47/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +010048 * The following function initializes the cpu_context 'ctx' for
Andrew Thoelke4e126072014-06-04 21:10:52 +010049 * first use, and sets the initial entrypoint state as specified by the
50 * entry_point_info structure.
51 *
52 * The security state to initialize is determined by the SECURE attribute
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +010053 * of the entry_point_info.
Andrew Thoelke4e126072014-06-04 21:10:52 +010054 *
55 * The EE and ST attributes are used to configure the endianess and secure
Soby Mathewb0082d22015-04-09 13:40:55 +010056 * timer availability for the new execution context.
Andrew Thoelke4e126072014-06-04 21:10:52 +010057 *
58 * To prepare the register state for entry call cm_prepare_el3_exit() and
59 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
60 * cm_e1_sysreg_context_restore().
61 ******************************************************************************/
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +010062void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke4e126072014-06-04 21:10:52 +010063{
Soby Mathewb0082d22015-04-09 13:40:55 +010064 unsigned int security_state;
David Cunado4168f2f2017-10-02 17:41:39 +010065 uint32_t scr_el3, pmcr_el0;
Andrew Thoelke4e126072014-06-04 21:10:52 +010066 el3_state_t *state;
67 gp_regs_t *gp_regs;
Varun Wadekarb6dd0b32018-05-08 10:52:36 -070068 unsigned long sctlr_elx, actlr_elx;
Andrew Thoelke4e126072014-06-04 21:10:52 +010069
Andrew Thoelke4e126072014-06-04 21:10:52 +010070 assert(ctx);
71
Soby Mathewb0082d22015-04-09 13:40:55 +010072 security_state = GET_SECURITY_STATE(ep->h.attr);
73
Andrew Thoelke4e126072014-06-04 21:10:52 +010074 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +000075 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke4e126072014-06-04 21:10:52 +010076
77 /*
David Cunadofee86532017-04-13 22:38:29 +010078 * SCR_EL3 was initialised during reset sequence in macro
79 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
80 * affect the next EL.
81 *
82 * The following fields are initially set to zero and then updated to
83 * the required value depending on the state of the SPSR_EL3 and the
84 * Security state and entrypoint attributes of the next EL.
Andrew Thoelke4e126072014-06-04 21:10:52 +010085 */
86 scr_el3 = read_scr();
87 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
88 SCR_ST_BIT | SCR_HCE_BIT);
David Cunadofee86532017-04-13 22:38:29 +010089 /*
90 * SCR_NS: Set the security state of the next EL.
91 */
Andrew Thoelke4e126072014-06-04 21:10:52 +010092 if (security_state != SECURE)
93 scr_el3 |= SCR_NS_BIT;
David Cunadofee86532017-04-13 22:38:29 +010094 /*
95 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
96 * Exception level as specified by SPSR.
97 */
Andrew Thoelke4e126072014-06-04 21:10:52 +010098 if (GET_RW(ep->spsr) == MODE_RW_64)
99 scr_el3 |= SCR_RW_BIT;
David Cunadofee86532017-04-13 22:38:29 +0100100 /*
101 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
102 * Secure timer registers to EL3, from AArch64 state only, if specified
103 * by the entrypoint attributes.
104 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100105 if (EP_GET_ST(ep->h.attr))
106 scr_el3 |= SCR_ST_BIT;
107
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700108#if !HANDLE_EA_EL3_FIRST
David Cunadofee86532017-04-13 22:38:29 +0100109 /*
110 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
111 * to EL3 when executing at a lower EL. When executing at EL3, External
112 * Aborts are taken to EL3.
113 */
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100114 scr_el3 &= ~SCR_EA_BIT;
115#endif
116
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000117#if FAULT_INJECTION_SUPPORT
118 /* Enable fault injection from lower ELs */
119 scr_el3 |= SCR_FIEN_BIT;
120#endif
121
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900122#ifdef IMAGE_BL31
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100123 /*
David Cunadofee86532017-04-13 22:38:29 +0100124 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ rounting as
125 * indicated by the interrupt routing model for BL31.
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100126 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100127 scr_el3 |= get_scr_el3_from_routing_model(security_state);
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100128#endif
Andrew Thoelke4e126072014-06-04 21:10:52 +0100129
130 /*
David Cunadofee86532017-04-13 22:38:29 +0100131 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
132 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
133 * next mode is Hyp.
134 */
135 if ((GET_RW(ep->spsr) == MODE_RW_64
136 && GET_EL(ep->spsr) == MODE_EL2)
137 || (GET_RW(ep->spsr) != MODE_RW_64
138 && GET_M32(ep->spsr) == MODE32_hyp)) {
139 scr_el3 |= SCR_HCE_BIT;
140 }
141
142 /*
143 * Initialise SCTLR_EL1 to the reset value corresponding to the target
144 * execution state setting all fields rather than relying of the hw.
145 * Some fields have architecturally UNKNOWN reset values and these are
146 * set to zero.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100147 *
David Cunadofee86532017-04-13 22:38:29 +0100148 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100149 *
David Cunadofee86532017-04-13 22:38:29 +0100150 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
151 * required by PSCI specification)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100152 */
153 sctlr_elx = EP_GET_EE(ep->h.attr) ? SCTLR_EE_BIT : 0;
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200154 if (GET_RW(ep->spsr) == MODE_RW_64)
155 sctlr_elx |= SCTLR_EL1_RES1;
Soby Mathewa993c422016-09-29 14:15:57 +0100156 else {
Soby Mathewa993c422016-09-29 14:15:57 +0100157 /*
David Cunadofee86532017-04-13 22:38:29 +0100158 * If the target execution state is AArch32 then the following
159 * fields need to be set.
160 *
161 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
162 * instructions are not trapped to EL1.
163 *
164 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
165 * instructions are not trapped to EL1.
166 *
167 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
168 * CP15DMB, CP15DSB, and CP15ISB instructions.
Soby Mathewa993c422016-09-29 14:15:57 +0100169 */
David Cunadofee86532017-04-13 22:38:29 +0100170 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
171 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
Soby Mathewa993c422016-09-29 14:15:57 +0100172 }
173
David Cunadofee86532017-04-13 22:38:29 +0100174 /*
175 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
David Cunado4168f2f2017-10-02 17:41:39 +0100176 * and other EL2 registers are set up by cm_preapre_ns_entry() as they
David Cunadofee86532017-04-13 22:38:29 +0100177 * are not part of the stored cpu_context.
178 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100179 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
180
Varun Wadekarb6dd0b32018-05-08 10:52:36 -0700181 /*
182 * Base the context ACTLR_EL1 on the current value, as it is
183 * implementation defined. The context restore process will write
184 * the value from the context to the actual register and can cause
185 * problems for processor cores that don't expect certain bits to
186 * be zero.
187 */
188 actlr_elx = read_actlr_el1();
189 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
190
David Cunado4168f2f2017-10-02 17:41:39 +0100191 if (security_state == SECURE) {
192 /*
193 * Initialise PMCR_EL0 for secure context only, setting all
194 * fields rather than relying on hw. Some fields are
195 * architecturally UNKNOWN on reset.
196 *
197 * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
198 * is recorded in PMOVSCLR_EL0[31], occurs on the increment
199 * that changes PMCCNTR_EL0[63] from 1 to 0.
200 *
201 * PMCR_EL0.DP: Set to one so that the cycle counter,
202 * PMCCNTR_EL0 does not count when event counting is prohibited.
203 *
204 * PMCR_EL0.X: Set to zero to disable export of events.
205 *
206 * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
207 * counts on every clock cycle.
208 */
209 pmcr_el0 = ((PMCR_EL0_RESET_VAL | PMCR_EL0_LC_BIT
210 | PMCR_EL0_DP_BIT)
211 & ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT));
212 write_ctx_reg(get_sysregs_ctx(ctx), CTX_PMCR_EL0, pmcr_el0);
213 }
214
Andrew Thoelke4e126072014-06-04 21:10:52 +0100215 /* Populate EL3 state so that we've the right context before doing ERET */
216 state = get_el3state_ctx(ctx);
217 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
218 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
219 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
220
221 /*
222 * Store the X0-X7 value from the entrypoint into the context
223 * Use memcpy as we are in control of the layout of the structures
224 */
225 gp_regs = get_gpregs_ctx(ctx);
226 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
227}
228
229/*******************************************************************************
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000230 * Enable architecture extensions on first entry to Non-secure world.
231 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
232 * it is zero.
233 ******************************************************************************/
234static void enable_extensions_nonsecure(int el2_unused)
235{
236#if IMAGE_BL31
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100237#if ENABLE_SPE_FOR_LOWER_ELS
238 spe_enable(el2_unused);
239#endif
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100240
241#if ENABLE_AMU
242 amu_enable(el2_unused);
243#endif
David Cunadoce88eee2017-10-20 11:30:57 +0100244
245#if ENABLE_SVE_FOR_NS
246 sve_enable(el2_unused);
247#endif
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100248
249#if ENABLE_MPAM_FOR_LOWER_ELS
250 mpam_enable(el2_unused);
251#endif
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000252#endif
253}
254
255/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +0100256 * The following function initializes the cpu_context for a CPU specified by
257 * its `cpu_idx` for first use, and sets the initial entrypoint state as
258 * specified by the entry_point_info structure.
259 ******************************************************************************/
260void cm_init_context_by_index(unsigned int cpu_idx,
261 const entry_point_info_t *ep)
262{
263 cpu_context_t *ctx;
264 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100265 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100266}
267
268/*******************************************************************************
269 * The following function initializes the cpu_context for the current CPU
270 * for first use, and sets the initial entrypoint state as specified by the
271 * entry_point_info structure.
272 ******************************************************************************/
273void cm_init_my_context(const entry_point_info_t *ep)
274{
275 cpu_context_t *ctx;
276 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100277 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100278}
279
280/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100281 * Prepare the CPU system registers for first entry into secure or normal world
282 *
283 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
284 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
285 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
286 * For all entries, the EL1 registers are initialized from the cpu_context
287 ******************************************************************************/
288void cm_prepare_el3_exit(uint32_t security_state)
289{
dp-armee3457b2017-05-23 09:32:49 +0100290 uint32_t sctlr_elx, scr_el3, mdcr_el2;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100291 cpu_context_t *ctx = cm_get_context(security_state);
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000292 int el2_unused = 0;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100293
294 assert(ctx);
295
296 if (security_state == NON_SECURE) {
297 scr_el3 = read_ctx_reg(get_el3state_ctx(ctx), CTX_SCR_EL3);
298 if (scr_el3 & SCR_HCE_BIT) {
299 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
300 sctlr_elx = read_ctx_reg(get_sysregs_ctx(ctx),
301 CTX_SCTLR_EL1);
Ken Kuang00eac152017-08-23 16:03:29 +0800302 sctlr_elx &= SCTLR_EE_BIT;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100303 sctlr_elx |= SCTLR_EL2_RES1;
304 write_sctlr_el2(sctlr_elx);
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000305 } else if (EL_IMPLEMENTED(2)) {
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000306 el2_unused = 1;
307
David Cunadofee86532017-04-13 22:38:29 +0100308 /*
309 * EL2 present but unused, need to disable safely.
310 * SCTLR_EL2 can be ignored in this case.
311 *
312 * Initialise all fields in HCR_EL2, except HCR_EL2.RW,
313 * to zero so that Non-secure operations do not trap to
314 * EL2.
315 *
316 * HCR_EL2.RW: Set this field to match SCR_EL3.RW
317 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100318 write_hcr_el2((scr_el3 & SCR_RW_BIT) ? HCR_RW_BIT : 0);
319
David Cunadofee86532017-04-13 22:38:29 +0100320 /*
321 * Initialise CPTR_EL2 setting all fields rather than
322 * relying on the hw. All fields have architecturally
323 * UNKNOWN reset values.
324 *
325 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
326 * accesses to the CPACR_EL1 or CPACR from both
327 * Execution states do not trap to EL2.
328 *
329 * CPTR_EL2.TTA: Set to zero so that Non-secure System
330 * register accesses to the trace registers from both
331 * Execution states do not trap to EL2.
332 *
333 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
334 * to SIMD and floating-point functionality from both
335 * Execution states do not trap to EL2.
336 */
337 write_cptr_el2(CPTR_EL2_RESET_VAL &
338 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
339 | CPTR_EL2_TFP_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100340
David Cunadofee86532017-04-13 22:38:29 +0100341 /*
342 * Initiliase CNTHCTL_EL2. All fields are
343 * architecturally UNKNOWN on reset and are set to zero
344 * except for field(s) listed below.
345 *
346 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to
347 * Hyp mode of Non-secure EL0 and EL1 accesses to the
348 * physical timer registers.
349 *
350 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
351 * Hyp mode of Non-secure EL0 and EL1 accesses to the
352 * physical counter registers.
353 */
354 write_cnthctl_el2(CNTHCTL_RESET_VAL |
355 EL1PCEN_BIT | EL1PCTEN_BIT);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100356
David Cunadofee86532017-04-13 22:38:29 +0100357 /*
358 * Initialise CNTVOFF_EL2 to zero as it resets to an
359 * architecturally UNKNOWN value.
360 */
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100361 write_cntvoff_el2(0);
362
David Cunadofee86532017-04-13 22:38:29 +0100363 /*
364 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
365 * MPIDR_EL1 respectively.
366 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100367 write_vpidr_el2(read_midr_el1());
368 write_vmpidr_el2(read_mpidr_el1());
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000369
370 /*
David Cunadofee86532017-04-13 22:38:29 +0100371 * Initialise VTTBR_EL2. All fields are architecturally
372 * UNKNOWN on reset.
373 *
374 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
375 * 2 address translation is disabled, cache maintenance
376 * operations depend on the VMID.
377 *
378 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
379 * translation is disabled.
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000380 */
David Cunadofee86532017-04-13 22:38:29 +0100381 write_vttbr_el2(VTTBR_RESET_VAL &
382 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
383 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
384
David Cunado5f55e282016-10-31 17:37:34 +0000385 /*
David Cunadofee86532017-04-13 22:38:29 +0100386 * Initialise MDCR_EL2, setting all fields rather than
387 * relying on hw. Some fields are architecturally
388 * UNKNOWN on reset.
389 *
390 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
391 * EL1 System register accesses to the Debug ROM
392 * registers are not trapped to EL2.
393 *
394 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
395 * System register accesses to the powerdown debug
396 * registers are not trapped to EL2.
397 *
398 * MDCR_EL2.TDA: Set to zero so that System register
399 * accesses to the debug registers do not trap to EL2.
400 *
401 * MDCR_EL2.TDE: Set to zero so that debug exceptions
402 * are not routed to EL2.
403 *
404 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
405 * Monitors.
406 *
407 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
408 * EL1 accesses to all Performance Monitors registers
409 * are not trapped to EL2.
410 *
411 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
412 * and EL1 accesses to the PMCR_EL0 or PMCR are not
413 * trapped to EL2.
414 *
415 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
416 * architecturally-defined reset value.
David Cunado5f55e282016-10-31 17:37:34 +0000417 */
dp-armee3457b2017-05-23 09:32:49 +0100418 mdcr_el2 = ((MDCR_EL2_RESET_VAL |
David Cunadofee86532017-04-13 22:38:29 +0100419 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
420 >> PMCR_EL0_N_SHIFT)) &
421 ~(MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT
422 | MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT
423 | MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT
424 | MDCR_EL2_TPMCR_BIT));
dp-armee3457b2017-05-23 09:32:49 +0100425
dp-armee3457b2017-05-23 09:32:49 +0100426 write_mdcr_el2(mdcr_el2);
427
David Cunadoc14b08e2016-11-25 00:21:59 +0000428 /*
David Cunadofee86532017-04-13 22:38:29 +0100429 * Initialise HSTR_EL2. All fields are architecturally
430 * UNKNOWN on reset.
431 *
432 * HSTR_EL2.T<n>: Set all these fields to zero so that
433 * Non-secure EL0 or EL1 accesses to System registers
434 * do not trap to EL2.
David Cunadoc14b08e2016-11-25 00:21:59 +0000435 */
David Cunadofee86532017-04-13 22:38:29 +0100436 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
David Cunadoc14b08e2016-11-25 00:21:59 +0000437 /*
David Cunadofee86532017-04-13 22:38:29 +0100438 * Initialise CNTHP_CTL_EL2. All fields are
439 * architecturally UNKNOWN on reset.
440 *
441 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
442 * physical timer and prevent timer interrupts.
David Cunadoc14b08e2016-11-25 00:21:59 +0000443 */
David Cunadofee86532017-04-13 22:38:29 +0100444 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
445 ~(CNTHP_CTL_ENABLE_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100446 }
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000447 enable_extensions_nonsecure(el2_unused);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100448 }
449
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100450 cm_el1_sysregs_context_restore(security_state);
451 cm_set_next_eret_context(security_state);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100452}
453
454/*******************************************************************************
Soby Mathew2ed46e92014-07-04 16:02:26 +0100455 * The next four functions are used by runtime services to save and restore
456 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +0000457 * state.
458 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +0000459void cm_el1_sysregs_context_save(uint32_t security_state)
460{
Dan Handleye2712bc2014-04-10 15:37:22 +0100461 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000462
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100463 ctx = cm_get_context(security_state);
Achin Gupta7aea9082014-02-01 07:51:28 +0000464 assert(ctx);
465
466 el1_sysregs_context_save(get_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100467
468#if IMAGE_BL31
469 if (security_state == SECURE)
470 PUBLISH_EVENT(cm_exited_secure_world);
471 else
472 PUBLISH_EVENT(cm_exited_normal_world);
473#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000474}
475
476void cm_el1_sysregs_context_restore(uint32_t security_state)
477{
Dan Handleye2712bc2014-04-10 15:37:22 +0100478 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000479
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100480 ctx = cm_get_context(security_state);
Achin Gupta7aea9082014-02-01 07:51:28 +0000481 assert(ctx);
482
483 el1_sysregs_context_restore(get_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100484
485#if IMAGE_BL31
486 if (security_state == SECURE)
487 PUBLISH_EVENT(cm_entering_secure_world);
488 else
489 PUBLISH_EVENT(cm_entering_normal_world);
490#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000491}
492
493/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100494 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
495 * given security state with the given entrypoint
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000496 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100497void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000498{
Dan Handleye2712bc2014-04-10 15:37:22 +0100499 cpu_context_t *ctx;
500 el3_state_t *state;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000501
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100502 ctx = cm_get_context(security_state);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000503 assert(ctx);
504
Andrew Thoelke4e126072014-06-04 21:10:52 +0100505 /* Populate EL3 state so that ERET jumps to the correct entry */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000506 state = get_el3state_ctx(ctx);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000507 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000508}
509
510/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100511 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
512 * pertaining to the given security state
Achin Gupta607084e2014-02-09 18:24:19 +0000513 ******************************************************************************/
Andrew Thoelke4e126072014-06-04 21:10:52 +0100514void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100515 uintptr_t entrypoint, uint32_t spsr)
Achin Gupta607084e2014-02-09 18:24:19 +0000516{
Dan Handleye2712bc2014-04-10 15:37:22 +0100517 cpu_context_t *ctx;
518 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +0000519
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100520 ctx = cm_get_context(security_state);
Achin Gupta607084e2014-02-09 18:24:19 +0000521 assert(ctx);
522
523 /* Populate EL3 state so that ERET jumps to the correct entry */
524 state = get_el3state_ctx(ctx);
525 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100526 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
Achin Gupta607084e2014-02-09 18:24:19 +0000527}
528
529/*******************************************************************************
Achin Gupta27b895e2014-05-04 18:38:28 +0100530 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
531 * pertaining to the given security state using the value and bit position
532 * specified in the parameters. It preserves all other bits.
533 ******************************************************************************/
534void cm_write_scr_el3_bit(uint32_t security_state,
535 uint32_t bit_pos,
536 uint32_t value)
537{
538 cpu_context_t *ctx;
539 el3_state_t *state;
540 uint32_t scr_el3;
541
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100542 ctx = cm_get_context(security_state);
Achin Gupta27b895e2014-05-04 18:38:28 +0100543 assert(ctx);
544
545 /* Ensure that the bit position is a valid one */
546 assert((1 << bit_pos) & SCR_VALID_BIT_MASK);
547
548 /* Ensure that the 'value' is only a bit wide */
549 assert(value <= 1);
550
551 /*
552 * Get the SCR_EL3 value from the cpu context, clear the desired bit
553 * and set it to its new value.
554 */
555 state = get_el3state_ctx(ctx);
556 scr_el3 = read_ctx_reg(state, CTX_SCR_EL3);
557 scr_el3 &= ~(1 << bit_pos);
558 scr_el3 |= value << bit_pos;
559 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
560}
561
562/*******************************************************************************
563 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
564 * given security state.
565 ******************************************************************************/
566uint32_t cm_get_scr_el3(uint32_t security_state)
567{
568 cpu_context_t *ctx;
569 el3_state_t *state;
570
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100571 ctx = cm_get_context(security_state);
Achin Gupta27b895e2014-05-04 18:38:28 +0100572 assert(ctx);
573
574 /* Populate EL3 state so that ERET jumps to the correct entry */
575 state = get_el3state_ctx(ctx);
576 return read_ctx_reg(state, CTX_SCR_EL3);
577}
578
579/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000580 * This function is used to program the context that's used for exception
581 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
582 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +0000583 ******************************************************************************/
584void cm_set_next_eret_context(uint32_t security_state)
585{
Dan Handleye2712bc2014-04-10 15:37:22 +0100586 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000587
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100588 ctx = cm_get_context(security_state);
Achin Gupta7aea9082014-02-01 07:51:28 +0000589 assert(ctx);
590
Andrew Thoelke4e126072014-06-04 21:10:52 +0100591 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +0000592}