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git01.mediatek.com / filogic / atf / 57eaae8c60da9cff13431eb27fa51807111f4533 / . / plat / nvidia / tegra / soc / t194 / platform_t194.mk
blob: 78766fcbed288544daac7a6f715b22c0b202130e [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]1#
Varun Wadekare9d69f72017-11-29 15:34:58 -0800[diff] [blame]2# Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# platform configs
Varun Wadekar19ecdb92017-12-01 09:24:12 -0800[diff] [blame]8ENABLE_CONSOLE_SPE := 1
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]9$(eval $(call add_define,ENABLE_CONSOLE_SPE))
10
Varun Wadekar602cf7e2018-04-03 13:10:48 -0700[diff] [blame]11ENABLE_STRICT_CHECKING_MODE := 1
Steven Kao8f4f1022017-12-13 06:39:15 +0800[diff] [blame]12$(eval $(call add_define,ENABLE_STRICT_CHECKING_MODE))
13
Varun Wadekar602cf7e2018-04-03 13:10:48 -0700[diff] [blame]14USE_GPC_DMA := 1
15$(eval $(call add_define,USE_GPC_DMA))
16
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]17RESET_TO_BL31 := 1
18
19PROGRAMMABLE_RESET_ADDRESS := 1
20
21COLD_BOOT_SINGLE_CPU := 1
22
23# platform settings
24TZDRAM_BASE := 0x40000000
25$(eval $(call add_define,TZDRAM_BASE))
26
Varun Wadekara07d1c72017-08-23 14:59:09 -0700[diff] [blame]27PLATFORM_CLUSTER_COUNT := 4
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]28$(eval $(call add_define,PLATFORM_CLUSTER_COUNT))
29
Varun Wadekara07d1c72017-08-23 14:59:09 -0700[diff] [blame]30PLATFORM_MAX_CPUS_PER_CLUSTER := 2
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]31$(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
32
Ajay Gupta81621092017-08-01 15:53:04 -0700[diff] [blame]33MAX_XLAT_TABLES := 25
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]34$(eval $(call add_define,MAX_XLAT_TABLES))
35
Steven Kao58d11942017-09-29 16:32:34 +0800[diff] [blame]36MAX_MMAP_REGIONS := 30
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]37$(eval $(call add_define,MAX_MMAP_REGIONS))
38
39# platform files
40PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
41
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]42BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
Varun Wadekar498d5012017-11-15 15:52:01 -0800[diff] [blame]43 lib/cpus/aarch64/denver.S \
steven kaoe5796062018-01-02 19:09:04 -0800[diff] [blame]44 ${COMMON_DIR}/drivers/bpmp_ipc/intf.c \
45 ${COMMON_DIR}/drivers/bpmp_ipc/ivc.c \
Varun Wadekar602cf7e2018-04-03 13:10:48 -0700[diff] [blame]46 ${COMMON_DIR}/drivers/gpcdma/gpcdma.c \
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]47 ${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
48 ${COMMON_DIR}/drivers/smmu/smmu.c \
49 ${SOC_DIR}/drivers/mce/mce.c \
Steven Kao2cdb6782017-01-05 17:04:40 +0800[diff] [blame]50 ${SOC_DIR}/drivers/mce/nvg.c \
51 ${SOC_DIR}/drivers/mce/aarch64/nvg_helpers.S \
Steven Kao530b2172017-06-23 16:18:58 +0800[diff] [blame]52 ${SOC_DIR}/drivers/se/se.c \
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]53 ${SOC_DIR}/plat_memctrl.c \
Varun Wadekarecd6a5a2018-04-09 17:48:58 -0700[diff] [blame]54 ${SOC_DIR}/plat_psci_handlers.c \
55 ${SOC_DIR}/plat_setup.c \
56 ${SOC_DIR}/plat_secondary.c \
Varun Wadekar00759902017-05-31 11:41:00 -0700[diff] [blame]57 ${SOC_DIR}/plat_sip_calls.c \
Varun Wadekar362a6b22017-11-10 11:04:42 -0800[diff] [blame]58 ${SOC_DIR}/plat_smmu.c \
59 ${SOC_DIR}/plat_trampoline.S
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700[diff] [blame]60
61ifeq (${ENABLE_CONSOLE_SPE},1)
62BL31_SOURCES += ${COMMON_DIR}/drivers/spe/shared_console.S
63endif