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git01.mediatek.com / filogic / atf / 56def63504e093b4af344d2e3e94c3ed0e5f2eee / . / plat / nvidia / tegra / include / t132 / tegra_def.h
blob: 6b87655e3cb4f3e50c7e11943535e432b7fdf033 [file] [log] [blame]
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]1/*
Steven Kao0cb8b332018-02-09 20:50:02 +0800[diff] [blame]2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Varun Wadekar1b0c1242018-05-15 11:24:59 -0700[diff] [blame]3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]4 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]5 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]6 */
7
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]8#ifndef TEGRA_DEF_H
9#define TEGRA_DEF_H
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]10
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]11#include <lib/utils_def.h>
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]12
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]13/*******************************************************************************
anzhou508d20d2020-07-21 16:22:44 +0800[diff] [blame]14 * Platform BL31 specific defines.
15 ******************************************************************************/
16#define BL31_SIZE U(0x40000)
17
18/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]19 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
20 * call as the `state-id` field in the 'power state' parameter.
21 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]22#define PSTATE_ID_SOC_POWERDN U(0xD)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]23
24/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]25 * Platform power states (used by PSCI framework)
26 *
27 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
28 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
29 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]30#define PLAT_MAX_RET_STATE U(1)
31#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]32
33/*******************************************************************************
Steven Kao0cb8b332018-02-09 20:50:02 +0800[diff] [blame]34 * Chip specific page table and MMU setup constants
35 ******************************************************************************/
36#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
37#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
38
39/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]40 * GIC memory map
41 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]42#define TEGRA_GICD_BASE U(0x50041000)
43#define TEGRA_GICC_BASE U(0x50042000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]44
45/*******************************************************************************
46 * Tegra micro-seconds timer constants
47 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]48#define TEGRA_TMRUS_BASE U(0x60005010)
49#define TEGRA_TMRUS_SIZE U(0x1000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]50
51/*******************************************************************************
52 * Tegra Clock and Reset Controller constants
53 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]54#define TEGRA_CAR_RESET_BASE U(0x60006000)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]55#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530[diff] [blame]56#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
Varun Wadekara59a7c52017-04-26 08:31:50 -0700[diff] [blame]57#define GPU_RESET_BIT (U(1) << 24)
Jeetesh Burman48fef882018-01-22 15:40:08 +0530[diff] [blame]58#define GPU_SET_BIT (U(1) << 24)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]59
60/*******************************************************************************
61 * Tegra Flow Controller constants
62 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]63#define TEGRA_FLOWCTRL_BASE U(0x60007000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]64
65/*******************************************************************************
66 * Tegra Secure Boot Controller constants
67 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]68#define TEGRA_SB_BASE U(0x6000C200)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]69
70/*******************************************************************************
71 * Tegra Exception Vectors constants
72 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]73#define TEGRA_EVP_BASE U(0x6000F000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]74
75/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]76 * Tegra Miscellaneous register constants
77 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]78#define TEGRA_MISC_BASE U(0x70000000)
79#define HARDWARE_REVISION_OFFSET U(0x804)
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]80
81/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]82 * Tegra UART controller base addresses
83 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]84#define TEGRA_UARTA_BASE U(0x70006000)
85#define TEGRA_UARTB_BASE U(0x70006040)
86#define TEGRA_UARTC_BASE U(0x70006200)
87#define TEGRA_UARTD_BASE U(0x70006300)
88#define TEGRA_UARTE_BASE U(0x70006400)
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]89
90/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]91 * Tegra Power Mgmt Controller constants
92 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]93#define TEGRA_PMC_BASE U(0x7000E400)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]94
95/*******************************************************************************
96 * Tegra Memory Controller constants
97 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]98#define TEGRA_MC_BASE U(0x70019000)
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]99
Harvey Hsieh359be952017-08-21 15:01:53 +0800[diff] [blame]100/* Memory Controller Interrupt Status */
101#define MC_INTSTATUS 0x00U
102
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]103/* TZDRAM carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]104#define MC_SECURITY_CFG0_0 U(0x70)
105#define MC_SECURITY_CFG1_0 U(0x74)
106#define MC_SECURITY_CFG3_0 U(0x9BC)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]107
108/* Video Memory carveout configuration registers */
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]109#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
110#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
111#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
Anthony Zhou41eac8a2019-12-04 14:58:23 +0800[diff] [blame]112#define MC_VIDEO_PROTECT_REG_CTRL U(0x650)
113#define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED U(3)
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]114
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]115/*******************************************************************************
116 * Tegra TZRAM constants
117 ******************************************************************************/
Varun Wadekar761ca732017-04-24 14:17:12 -0700[diff] [blame]118#define TEGRA_TZRAM_BASE U(0x7C010000)
119#define TEGRA_TZRAM_SIZE U(0x10000)
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]120
Varun Wadekar1b0c1242018-05-15 11:24:59 -0700[diff] [blame]121/*******************************************************************************
122 * Tegra DRAM memory base address
123 ******************************************************************************/
124#define TEGRA_DRAM_BASE ULL(0x80000000)
125#define TEGRA_DRAM_END ULL(0x27FFFFFFF)
126
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]127#endif /* TEGRA_DEF_H */