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git01.mediatek.com / filogic / atf / 37c70760b973d55f61fa6e0adfba6d7af1c369b0 / . / plat / intel / soc / common / include / socfpga_sip_svc.h
blob: aab7bbf35c8831c04961fb1aa4920e1cd5487ea9 [file] [log] [blame]
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]1/*
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800[diff] [blame]2 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef SOCFPGA_SIP_SVC_H
8#define SOCFPGA_SIP_SVC_H
9
10
11/* SiP status response */
12#define INTEL_SIP_SMC_STATUS_OK 0
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]13#define INTEL_SIP_SMC_STATUS_BUSY 0x1
14#define INTEL_SIP_SMC_STATUS_REJECTED 0x2
Abdul Halim, Muhammad Hadi Asyrafi25f623e2020-02-27 10:23:48 +0800[diff] [blame]15#define INTEL_SIP_SMC_STATUS_ERROR 0x4
16#define INTEL_SIP_SMC_RSU_ERROR 0x7
17
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800[diff] [blame]18/* SiP mailbox error code */
19#define GENERIC_RESPONSE_ERROR 0x3FF
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]20
21/* SMC SiP service function identifier */
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]22
23/* FPGA Reconfig */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]24#define INTEL_SIP_SMC_FPGA_CONFIG_START 0xC2000001
25#define INTEL_SIP_SMC_FPGA_CONFIG_WRITE 0x42000002
26#define INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE 0xC2000003
27#define INTEL_SIP_SMC_FPGA_CONFIG_ISDONE 0xC2000004
28#define INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM 0xC2000005
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]29
30/* Secure Register Access */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]31#define INTEL_SIP_SMC_REG_READ 0xC2000007
32#define INTEL_SIP_SMC_REG_WRITE 0xC2000008
33#define INTEL_SIP_SMC_REG_UPDATE 0xC2000009
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]34
35/* Remote System Update */
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]36#define INTEL_SIP_SMC_RSU_STATUS 0xC200000B
37#define INTEL_SIP_SMC_RSU_UPDATE 0xC200000C
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]38#define INTEL_SIP_SMC_RSU_NOTIFY 0xC200000E
39#define INTEL_SIP_SMC_RSU_RETRY_COUNTER 0xC200000F
Sieu Mun Tang9f22cbf2022-03-02 11:04:09 +0800[diff] [blame]40#define INTEL_SIP_SMC_RSU_DCMF_VERSION 0xC2000010
41#define INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION 0xC2000011
Chee Hong Ang681631b2020-07-01 14:22:25 +0800[diff] [blame]42#define INTEL_SIP_SMC_RSU_MAX_RETRY 0xC2000012
43#define INTEL_SIP_SMC_RSU_COPY_MAX_RETRY 0xC2000013
Sieu Mun Tange6d5de92022-04-28 22:21:01 +0800[diff] [blame]44#define INTEL_SIP_SMC_RSU_DCMF_STATUS 0xC2000014
45#define INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS 0xC2000015
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]46
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800[diff] [blame]47
48/* ECC */
49#define INTEL_SIP_SMC_ECC_DBE 0xC200000D
50
Sieu Mun Tanga34b8812022-03-17 03:11:55 +0800[diff] [blame]51/* Generic Command */
52#define INTEL_SIP_SMC_GET_ROM_PATCH_SHA384 0xC2000040
53
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]54/* Send Mailbox Command */
Hadi Asyrafia33e8102019-12-17 19:30:41 +0800[diff] [blame]55#define INTEL_SIP_SMC_MBOX_SEND_CMD 0xC200001E
Abdul Halim, Muhammad Hadi Asyrafib30ce3f2020-06-18 16:21:29 +0800[diff] [blame]56#define INTEL_SIP_SMC_HPS_SET_BRIDGES 0xC2000032
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]57
Abdul Halim, Muhammad Hadi Asyrafiec164b62020-05-14 14:53:29 +0800[diff] [blame]58
59/* SiP Definitions */
60
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800[diff] [blame]61/* ECC DBE */
62#define WARM_RESET_WFI_FLAG BIT(31)
63#define SYSMGR_ECC_DBE_COLD_RST_MASK (SYSMGR_ECC_OCRAM_MASK |\
64 SYSMGR_ECC_DDR0_MASK |\
65 SYSMGR_ECC_DDR1_MASK)
66
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +0800[diff] [blame]67/* Non-mailbox SMC Call */
68#define INTEL_SIP_SMC_SVC_VERSION 0xC2000200
69
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]70/* SMC function IDs for SiP Service queries */
71#define SIP_SVC_CALL_COUNT 0x8200ff00
72#define SIP_SVC_UID 0x8200ff01
73#define SIP_SVC_VERSION 0x8200ff03
74
75/* SiP Service Calls version numbers */
Sieu Mun Tangf9cb6572022-04-27 18:24:06 +0800[diff] [blame]76#define SIP_SVC_VERSION_MAJOR 1
77#define SIP_SVC_VERSION_MINOR 0
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]78
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800[diff] [blame]79
80/* Structure Definitions */
81struct fpga_config_info {
82 uint32_t addr;
83 int size;
84 int size_written;
85 uint32_t write_requested;
86 int subblocks_sent;
87 int block_number;
88};
89
Abdul Halim, Muhammad Hadi Asyrafib251c332020-05-29 12:13:17 +0800[diff] [blame]90typedef enum {
91 FULL_CONFIG = 0,
92 PARTIAL_CONFIG,
93} config_type;
94
Abdul Halim, Muhammad Hadi Asyrafi20a07f32020-05-18 11:16:48 +0800[diff] [blame]95/* Function Definitions */
96
97bool is_address_in_ddr_range(uint64_t addr, uint64_t size);
98
Sieu Mun Tangdbcc2cf2022-03-07 12:13:04 +0800[diff] [blame]99/* ECC DBE */
100bool cold_reset_for_ecc_dbe(void);
101uint32_t intel_ecc_dbe_notification(uint64_t dbe_value);
102
Hadi Asyrafiab1132f2019-10-22 10:31:45 +0800[diff] [blame]103#endif /* SOCFPGA_SIP_SVC_H */