| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 1 | /* |
| Govindraj Raja | eee28e7 | 2023-08-01 15:52:40 -0500 | [diff] [blame] | 2 | * Copyright (c) 2019-2023, Arm Limited. All rights reserved. |
| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef NEOVERSE_V1_H |
| 8 | #define NEOVERSE_V1_H |
| 9 | |
| 10 | #define NEOVERSE_V1_MIDR U(0x410FD400) |
| 11 | |
| Bipin Ravi | 8649974 | 2022-01-18 01:59:06 -0600 | [diff] [blame] | 12 | /* Neoverse V1 loop count for CVE-2022-23960 mitigation */ |
| 13 | #define NEOVERSE_V1_BHB_LOOP_COUNT U(32) |
| 14 | |
| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 15 | /******************************************************************************* |
| 16 | * CPU Extended Control register specific definitions. |
| 17 | ******************************************************************************/ |
| 18 | #define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4 |
| Juan Pablo Conde | 31c9337 | 2022-02-28 14:14:44 -0500 | [diff] [blame] | 19 | #define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0 |
| 20 | #define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2 |
| 21 | #define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3 |
| 22 | #define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1 |
| laurenw-arm | 6b56f96 | 2021-08-02 15:00:15 -0500 | [diff] [blame] | 23 | #define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) |
| laurenw-arm | 3c86d83 | 2021-08-02 13:22:32 -0500 | [diff] [blame] | 24 | #define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) |
| nayanpatel-arm | fc26ffe | 2021-09-28 13:41:03 -0700 | [diff] [blame] | 25 | #define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) |
| 26 | #define CPUECTLR_EL1_PF_MODE_LSB U(6) |
| 27 | #define CPUECTLR_EL1_PF_MODE_WIDTH U(2) |
| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 28 | |
| 29 | /******************************************************************************* |
| 30 | * CPU Power Control register specific definitions |
| 31 | ******************************************************************************/ |
| 32 | #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 |
| 33 | #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) |
| 34 | |
| johpow01 | c73b03c | 2021-05-03 15:33:39 -0500 | [diff] [blame] | 35 | /******************************************************************************* |
| 36 | * CPU Auxiliary Control register specific definitions. |
| 37 | ******************************************************************************/ |
| 38 | #define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 |
| Bipin Ravi | 971938f | 2022-06-08 16:28:46 -0500 | [diff] [blame] | 39 | #define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1) |
| johpow01 | c73b03c | 2021-05-03 15:33:39 -0500 | [diff] [blame] | 40 | #define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) |
| laurenw-arm | b1923e9 | 2021-08-02 14:40:08 -0500 | [diff] [blame] | 41 | #define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28) |
| Bipin Ravi | b4cb31f | 2022-06-14 17:09:23 -0500 | [diff] [blame] | 42 | #define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40) |
| johpow01 | c73b03c | 2021-05-03 15:33:39 -0500 | [diff] [blame] | 43 | |
| Sona Mathew | fe405d0 | 2023-01-11 17:04:24 -0600 | [diff] [blame] | 44 | #define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2 |
| Arvind Ram Prakash | 29cbe72 | 2023-07-21 16:01:22 -0500 | [diff] [blame] | 45 | #define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47) |
| Sona Mathew | fe405d0 | 2023-01-11 17:04:24 -0600 | [diff] [blame] | 46 | |
| Sona Mathew | 2ef5db7 | 2023-03-02 15:07:55 -0600 | [diff] [blame] | 47 | #define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0 |
| Arvind Ram Prakash | 29cbe72 | 2023-07-21 16:01:22 -0500 | [diff] [blame] | 48 | #define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55) |
| 49 | #define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56) |
| Sona Mathew | 2ef5db7 | 2023-03-02 15:07:55 -0600 | [diff] [blame] | 50 | |
| Jimmy Brisson | 958a0b1 | 2020-09-30 15:28:03 -0500 | [diff] [blame] | 51 | #endif /* NEOVERSE_V1_H */ |