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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Roberto Vargas1a6eed32018-02-12 12:36:17 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef GICV3_H
8#define GICV3_H
Achin Gupta92712a52015-09-03 14:18:02 +01009
10/*******************************************************************************
11 * GICv3 miscellaneous definitions
12 ******************************************************************************/
13/* Interrupt group definitions */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010014#define INTR_GROUP1S U(0)
15#define INTR_GROUP0 U(1)
16#define INTR_GROUP1NS U(2)
Achin Gupta92712a52015-09-03 14:18:02 +010017
18/* Interrupt IDs reported by the HPPIR and IAR registers */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010019#define PENDING_G1S_INTID U(1020)
20#define PENDING_G1NS_INTID U(1021)
Achin Gupta92712a52015-09-03 14:18:02 +010021
22/* Constant to categorize LPI interrupt */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010023#define MIN_LPI_ID U(8192)
Achin Gupta92712a52015-09-03 14:18:02 +010024
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010025/* GICv3 can only target up to 16 PEs with SGI */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010026#define GICV3_MAX_SGI_TARGETS U(16)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +010027
Achin Gupta92712a52015-09-03 14:18:02 +010028/*******************************************************************************
29 * GICv3 specific Distributor interface register offsets and constants.
30 ******************************************************************************/
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010031#define GICD_STATUSR U(0x10)
32#define GICD_SETSPI_NSR U(0x40)
33#define GICD_CLRSPI_NSR U(0x48)
34#define GICD_SETSPI_SR U(0x50)
35#define GICD_CLRSPI_SR U(0x50)
36#define GICD_IGRPMODR U(0xd00)
Soby Mathewaaf71c82016-07-26 17:46:56 +010037/*
38 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and
39 * n >= 32, making the effective offset as 0x6100.
40 */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010041#define GICD_IROUTER U(0x6000)
42#define GICD_PIDR2_GICV3 U(0xffe8)
Achin Gupta92712a52015-09-03 14:18:02 +010043
44#define IGRPMODR_SHIFT 5
45
46/* GICD_CTLR bit definitions */
47#define CTLR_ENABLE_G1NS_SHIFT 1
48#define CTLR_ENABLE_G1S_SHIFT 2
49#define CTLR_ARE_S_SHIFT 4
50#define CTLR_ARE_NS_SHIFT 5
51#define CTLR_DS_SHIFT 6
52#define CTLR_E1NWF_SHIFT 7
53#define GICD_CTLR_RWP_SHIFT 31
54
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010055#define CTLR_ENABLE_G1NS_MASK U(0x1)
56#define CTLR_ENABLE_G1S_MASK U(0x1)
57#define CTLR_ARE_S_MASK U(0x1)
58#define CTLR_ARE_NS_MASK U(0x1)
59#define CTLR_DS_MASK U(0x1)
60#define CTLR_E1NWF_MASK U(0x1)
61#define GICD_CTLR_RWP_MASK U(0x1)
Achin Gupta92712a52015-09-03 14:18:02 +010062
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010063#define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
64#define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
65#define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
66#define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
67#define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
68#define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
69#define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +010070
71/* GICD_IROUTER shifts and masks */
Soby Mathew327548c2017-07-13 15:19:51 +010072#define IROUTER_SHIFT 0
Achin Gupta92712a52015-09-03 14:18:02 +010073#define IROUTER_IRM_SHIFT 31
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010074#define IROUTER_IRM_MASK U(0x1)
Achin Gupta92712a52015-09-03 14:18:02 +010075
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010076#define GICV3_IRM_PE U(0)
77#define GICV3_IRM_ANY U(1)
Jeenu Viswambharandce70b32017-09-22 08:32:09 +010078
Soby Mathew327548c2017-07-13 15:19:51 +010079#define NUM_OF_DIST_REGS 30
80
Achin Gupta92712a52015-09-03 14:18:02 +010081/*******************************************************************************
82 * GICv3 Re-distributor interface registers & constants
83 ******************************************************************************/
84#define GICR_PCPUBASE_SHIFT 0x11
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010085#define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
86#define GICR_CTLR U(0x0)
Andrew F. Davis75ad53f2019-01-22 12:39:31 -060087#define GICR_IIDR U(0x04)
Antonio Nino Diaz2e590712018-08-24 11:46:33 +010088#define GICR_TYPER U(0x08)
89#define GICR_WAKER U(0x14)
90#define GICR_PROPBASER U(0x70)
91#define GICR_PENDBASER U(0x78)
92#define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + U(0x80))
93#define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100))
94#define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + U(0x180))
95#define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + U(0x200))
96#define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + U(0x280))
97#define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + U(0x300))
98#define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + U(0x380))
99#define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + U(0x400))
100#define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + U(0xc00))
101#define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + U(0xc04))
102#define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00))
103#define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00))
Achin Gupta92712a52015-09-03 14:18:02 +0100104
105/* GICR_CTLR bit definitions */
Soby Mathew327548c2017-07-13 15:19:51 +0100106#define GICR_CTLR_UWP_SHIFT 31
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100107#define GICR_CTLR_UWP_MASK U(0x1)
108#define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +0100109#define GICR_CTLR_RWP_SHIFT 3
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100110#define GICR_CTLR_RWP_MASK U(0x1)
111#define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT)
112#define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
Achin Gupta92712a52015-09-03 14:18:02 +0100113
114/* GICR_WAKER bit definitions */
115#define WAKER_CA_SHIFT 2
116#define WAKER_PS_SHIFT 1
117
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100118#define WAKER_CA_MASK U(0x1)
119#define WAKER_PS_MASK U(0x1)
Achin Gupta92712a52015-09-03 14:18:02 +0100120
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100121#define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT)
122#define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +0100123
124/* GICR_TYPER bit definitions */
125#define TYPER_AFF_VAL_SHIFT 32
126#define TYPER_PROC_NUM_SHIFT 8
127#define TYPER_LAST_SHIFT 4
128
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100129#define TYPER_AFF_VAL_MASK U(0xffffffff)
130#define TYPER_PROC_NUM_MASK U(0xffff)
131#define TYPER_LAST_MASK U(0x1)
Achin Gupta92712a52015-09-03 14:18:02 +0100132
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100133#define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +0100134
Soby Mathew327548c2017-07-13 15:19:51 +0100135#define NUM_OF_REDIST_REGS 30
136
Achin Gupta92712a52015-09-03 14:18:02 +0100137/*******************************************************************************
138 * GICv3 CPU interface registers & constants
139 ******************************************************************************/
140/* ICC_SRE bit definitions*/
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100141#define ICC_SRE_EN_BIT BIT_32(3)
142#define ICC_SRE_DIB_BIT BIT_32(2)
143#define ICC_SRE_DFB_BIT BIT_32(1)
144#define ICC_SRE_SRE_BIT BIT_32(0)
Achin Gupta92712a52015-09-03 14:18:02 +0100145
146/* ICC_IGRPEN1_EL3 bit definitions */
147#define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
148#define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
149
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100150#define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
151#define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +0100152
153/* ICC_IGRPEN0_EL1 bit definitions */
154#define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100155#define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
Achin Gupta92712a52015-09-03 14:18:02 +0100156
157/* ICC_HPPIR0_EL1 bit definitions */
158#define HPPIR0_EL1_INTID_SHIFT 0
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100159#define HPPIR0_EL1_INTID_MASK U(0xffffff)
Achin Gupta92712a52015-09-03 14:18:02 +0100160
161/* ICC_HPPIR1_EL1 bit definitions */
162#define HPPIR1_EL1_INTID_SHIFT 0
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100163#define HPPIR1_EL1_INTID_MASK U(0xffffff)
Achin Gupta92712a52015-09-03 14:18:02 +0100164
165/* ICC_IAR0_EL1 bit definitions */
166#define IAR0_EL1_INTID_SHIFT 0
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100167#define IAR0_EL1_INTID_MASK U(0xffffff)
Achin Gupta92712a52015-09-03 14:18:02 +0100168
169/* ICC_IAR1_EL1 bit definitions */
170#define IAR1_EL1_INTID_SHIFT 0
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100171#define IAR1_EL1_INTID_MASK U(0xffffff)
Achin Gupta92712a52015-09-03 14:18:02 +0100172
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100173/* ICC SGI macros */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100174#define SGIR_TGT_MASK ULL(0xffff)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100175#define SGIR_AFF1_SHIFT 16
176#define SGIR_INTID_SHIFT 24
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100177#define SGIR_INTID_MASK ULL(0xf)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100178#define SGIR_AFF2_SHIFT 32
179#define SGIR_IRM_SHIFT 40
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100180#define SGIR_IRM_MASK ULL(0x1)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100181#define SGIR_AFF3_SHIFT 48
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100182#define SGIR_AFF_MASK ULL(0xf)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100183
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100184#define SGIR_IRM_TO_AFF U(0)
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100185
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100186#define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
187 ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
188 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
189 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
190 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
191 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
192 ((_tgt) & SGIR_TGT_MASK))
Jeenu Viswambharanab14e9b2017-09-22 08:32:09 +0100193
Soby Mathewf6f1a322017-07-18 16:12:45 +0100194/*****************************************************************************
195 * GICv3 ITS registers and constants
196 *****************************************************************************/
197
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100198#define GITS_CTLR U(0x0)
199#define GITS_IIDR U(0x4)
200#define GITS_TYPER U(0x8)
201#define GITS_CBASER U(0x80)
202#define GITS_CWRITER U(0x88)
203#define GITS_CREADR U(0x90)
204#define GITS_BASER U(0x100)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100205
206/* GITS_CTLR bit definitions */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100207#define GITS_CTLR_ENABLED_BIT BIT_32(0)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100208#define GITS_CTLR_QUIESCENT_SHIFT 31
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100209#define GITS_CTLR_QUIESCENT_BIT BIT_32(GITS_CTLR_QUIESCENT_SHIFT)
Soby Mathewf6f1a322017-07-18 16:12:45 +0100210
Achin Gupta92712a52015-09-03 14:18:02 +0100211#ifndef __ASSEMBLY__
212
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100213#include <stdbool.h>
Achin Gupta92712a52015-09-03 14:18:02 +0100214#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000215
216#include <arch_helpers.h>
217#include <common/interrupt_props.h>
218#include <drivers/arm/gic_common.h>
219#include <lib/utils_def.h>
Achin Gupta92712a52015-09-03 14:18:02 +0100220
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100221static inline bool gicv3_is_intr_id_special_identifier(unsigned int id)
222{
223 return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT);
224}
Achin Gupta92712a52015-09-03 14:18:02 +0100225
226/*******************************************************************************
227 * Helper GICv3 macros for SEL1
228 ******************************************************************************/
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100229static inline uint32_t gicv3_acknowledge_interrupt_sel1(void)
230{
231 return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK;
232}
Achin Gupta92712a52015-09-03 14:18:02 +0100233
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100234static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void)
235{
236 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
237}
238
239static inline void gicv3_end_of_interrupt_sel1(unsigned int id)
240{
241 write_icc_eoir1_el1(id);
242}
Achin Gupta92712a52015-09-03 14:18:02 +0100243
244/*******************************************************************************
245 * Helper GICv3 macros for EL3
246 ******************************************************************************/
Antonio Nino Diazdd4e59e2018-08-13 15:29:29 +0100247static inline uint32_t gicv3_acknowledge_interrupt(void)
248{
249 return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK;
250}
251
252static inline void gicv3_end_of_interrupt(unsigned int id)
253{
254 return write_icc_eoir0_el1(id);
255}
Achin Gupta92712a52015-09-03 14:18:02 +0100256
Soby Mathew327548c2017-07-13 15:19:51 +0100257/*
258 * This macro returns the total number of GICD registers corresponding to
259 * the name.
260 */
261#define GICD_NUM_REGS(reg_name) \
262 DIV_ROUND_UP_2EVAL(TOTAL_SPI_INTR_NUM, (1 << reg_name ## _SHIFT))
263
264#define GICR_NUM_REGS(reg_name) \
265 DIV_ROUND_UP_2EVAL(TOTAL_PCPU_INTR_NUM, (1 << reg_name ## _SHIFT))
266
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +0100267/* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
Antonio Nino Diaz2e590712018-08-24 11:46:33 +0100268#define INT_ID_MASK U(0xffffff)
Jeenu Viswambharan055af4b2017-10-24 15:13:59 +0100269
Achin Gupta92712a52015-09-03 14:18:02 +0100270/*******************************************************************************
271 * This structure describes some of the implementation defined attributes of the
272 * GICv3 IP. It is used by the platform port to specify these attributes in order
273 * to initialise the GICV3 driver. The attributes are described below.
274 *
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100275 * The 'gicd_base' field contains the base address of the Distributor interface
276 * programmer's view.
277 *
278 * The 'gicr_base' field contains the base address of the Re-distributor
279 * interface programmer's view.
Achin Gupta92712a52015-09-03 14:18:02 +0100280 *
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100281 * The 'interrupt_props' field is a pointer to an array that enumerates secure
282 * interrupts and their properties. If this field is not NULL, both
283 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
Achin Gupta92712a52015-09-03 14:18:02 +0100284 *
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100285 * The 'interrupt_props_num' field contains the number of entries in the
286 * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num'
287 * and 'g1s_interrupt_num' are ignored.
Achin Gupta92712a52015-09-03 14:18:02 +0100288 *
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100289 * The 'rdistif_num' field contains the number of Redistributor interfaces the
290 * GIC implements. This is equal to the number of CPUs or CPU interfaces
291 * instantiated in the GIC.
Achin Gupta92712a52015-09-03 14:18:02 +0100292 *
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100293 * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for
294 * storing the base address of the Redistributor interface frame of each CPU in
295 * the system. The size of the array = 'rdistif_num'. The base addresses are
296 * detected during driver initialisation.
297 *
298 * The 'mpidr_to_core_pos' field is a pointer to a hash function which the
299 * driver will use to convert an MPIDR value to a linear core index. This index
300 * will be used for accessing the 'rdistif_base_addrs' array. This is an
301 * optional field. A GICv3 implementation maps each MPIDR to a linear core index
302 * as well. This mapping can be found by reading the "Affinity Value" and
303 * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
304 * "Processor Numbers" are suitable to index into an array to access core
305 * specific information. If this not the case, the platform port must provide a
306 * hash function. Otherwise, the "Processor Number" field will be used to access
307 * the array elements.
Achin Gupta92712a52015-09-03 14:18:02 +0100308 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100309typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
Achin Gupta92712a52015-09-03 14:18:02 +0100310
311typedef struct gicv3_driver_data {
312 uintptr_t gicd_base;
313 uintptr_t gicr_base;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100314 const interrupt_prop_t *interrupt_props;
315 unsigned int interrupt_props_num;
Achin Gupta92712a52015-09-03 14:18:02 +0100316 unsigned int rdistif_num;
317 uintptr_t *rdistif_base_addrs;
318 mpidr_hash_fn mpidr_to_core_pos;
319} gicv3_driver_data_t;
320
Soby Mathew327548c2017-07-13 15:19:51 +0100321typedef struct gicv3_redist_ctx {
322 /* 64 bits registers */
323 uint64_t gicr_propbaser;
324 uint64_t gicr_pendbaser;
325
326 /* 32 bits registers */
327 uint32_t gicr_ctlr;
328 uint32_t gicr_igroupr0;
329 uint32_t gicr_isenabler0;
330 uint32_t gicr_ispendr0;
331 uint32_t gicr_isactiver0;
332 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)];
333 uint32_t gicr_icfgr0;
334 uint32_t gicr_icfgr1;
335 uint32_t gicr_igrpmodr0;
336 uint32_t gicr_nsacr;
337} gicv3_redist_ctx_t;
338
339typedef struct gicv3_dist_ctx {
340 /* 64 bits registers */
341 uint64_t gicd_irouter[TOTAL_SPI_INTR_NUM];
342
343 /* 32 bits registers */
344 uint32_t gicd_ctlr;
345 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)];
346 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)];
347 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)];
348 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)];
349 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)];
350 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)];
351 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)];
352 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)];
353} gicv3_dist_ctx_t;
354
Soby Mathewf6f1a322017-07-18 16:12:45 +0100355typedef struct gicv3_its_ctx {
356 /* 64 bits registers */
357 uint64_t gits_cbaser;
358 uint64_t gits_cwriter;
359 uint64_t gits_baser[8];
360
361 /* 32 bits registers */
362 uint32_t gits_ctlr;
363} gicv3_its_ctx_t;
364
Achin Gupta92712a52015-09-03 14:18:02 +0100365/*******************************************************************************
366 * GICv3 EL3 driver API
367 ******************************************************************************/
368void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
369void gicv3_distif_init(void);
370void gicv3_rdistif_init(unsigned int proc_num);
Jeenu Viswambharan76647d52016-12-09 11:03:15 +0000371void gicv3_rdistif_on(unsigned int proc_num);
372void gicv3_rdistif_off(unsigned int proc_num);
Achin Gupta92712a52015-09-03 14:18:02 +0100373void gicv3_cpuif_enable(unsigned int proc_num);
374void gicv3_cpuif_disable(unsigned int proc_num);
375unsigned int gicv3_get_pending_interrupt_type(void);
376unsigned int gicv3_get_pending_interrupt_id(void);
377unsigned int gicv3_get_interrupt_type(unsigned int id,
378 unsigned int proc_num);
Soby Mathew327548c2017-07-13 15:19:51 +0100379void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx);
380void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx);
381/*
382 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if
383 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no
384 * implementation-defined sequence is needed at these steps, an empty function
385 * can be provided.
386 */
387void gicv3_distif_post_restore(unsigned int proc_num);
388void gicv3_distif_pre_save(unsigned int proc_num);
389void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx);
390void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx);
Soby Mathewf6f1a322017-07-18 16:12:45 +0100391void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx);
392void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx);
Achin Gupta92712a52015-09-03 14:18:02 +0100393
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100394unsigned int gicv3_get_running_priority(void);
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100395unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num);
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100396void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num);
397void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num);
Jeenu Viswambharan447b89d2017-09-22 08:32:09 +0100398void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
399 unsigned int priority);
Jeenu Viswambharanc06f05c2017-09-22 08:32:09 +0100400void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
Roberto Vargas1a6eed32018-02-12 12:36:17 +0000401 unsigned int type);
Antonio Nino Diazca994e72018-08-21 10:02:33 +0100402void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target);
Jeenu Viswambharandce70b32017-09-22 08:32:09 +0100403void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
404 u_register_t mpidr);
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100405void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);
406void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
Jeenu Viswambharan62505072017-09-22 08:32:09 +0100407unsigned int gicv3_set_pmr(unsigned int mask);
Jeenu Viswambharanb1e957e2017-09-22 08:32:09 +0100408
Achin Gupta92712a52015-09-03 14:18:02 +0100409#endif /* __ASSEMBLY__ */
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000410#endif /* GICV3_H */