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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Vijayenthiran Subramaniam8af18432019-10-22 15:46:14 +05302 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef CSS_DEF_H
8#define CSS_DEF_H
Dan Handley9df48042015-03-19 18:58:55 +00009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/interrupt_props.h>
11#include <drivers/arm/gic_common.h>
12#include <drivers/arm/tzc400.h>
13
Dan Handley9df48042015-03-19 18:58:55 +000014/*************************************************************************
15 * Definitions common to all ARM Compute SubSystems (CSS)
16 *************************************************************************/
Dan Handley9df48042015-03-19 18:58:55 +000017#define NSROM_BASE 0x1f000000
18#define NSROM_SIZE 0x00001000
19
20/* Following covers CSS Peripherals excluding NSROM and NSRAM */
21#define CSS_DEVICE_BASE 0x20000000
22#define CSS_DEVICE_SIZE 0x0e000000
Dan Handley9df48042015-03-19 18:58:55 +000023
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010024/* System Security Control Registers */
25#define SSC_REG_BASE 0x2a420000
26#define SSC_GPRETN (SSC_REG_BASE + 0x030)
27
Chandni Cherukuri346c7ca2018-09-16 21:05:49 +053028/* System ID Registers Unit */
29#define SID_REG_BASE 0x2a4a0000
30#define SID_SYSTEM_ID_OFFSET 0x40
31#define SID_SYSTEM_CFG_OFFSET 0x70
Vijayenthiran Subramaniam8af18432019-10-22 15:46:14 +053032#define SID_NODE_ID_OFFSET 0x60
33#define SID_CHIP_ID_MASK 0xFF
34#define SID_MULTI_CHIP_MODE_MASK 0x100
35#define SID_MULTI_CHIP_MODE_SHIFT 8
Chandni Cherukuri346c7ca2018-09-16 21:05:49 +053036
Dan Handley9df48042015-03-19 18:58:55 +000037/* The slave_bootsecure controls access to GPU, DMC and CS. */
38#define CSS_NIC400_SLAVE_BOOTSECURE 8
39
40/* Interrupt handling constants */
41#define CSS_IRQ_MHU 69
42#define CSS_IRQ_GPU_SMMU_0 71
Dan Handley9df48042015-03-19 18:58:55 +000043#define CSS_IRQ_TZC 80
44#define CSS_IRQ_TZ_WDOG 86
Vikram Kanigirif3bcea22015-06-24 17:51:09 +010045#define CSS_IRQ_SEC_SYS_TIMER 91
Dan Handley9df48042015-03-19 18:58:55 +000046
Soby Mathew1ced6b82017-06-12 12:37:10 +010047/* MHU register offsets */
48#define MHU_CPU_INTR_S_SET_OFFSET 0x308
49
Sandrine Bailleux761bba32015-04-29 13:02:46 +010050/*
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010051 * Define a list of Group 1 Secure interrupt properties as per GICv3
52 * terminology. On a GICv2 system or mode, the interrupts will be treated as
53 * Group 0 interrupts.
Achin Gupta1fa7eb62015-11-03 14:18:34 +000054 */
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010055#define CSS_G1S_IRQ_PROPS(grp) \
56 INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \
57 GIC_INTR_CFG_LEVEL), \
58 INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
59 GIC_INTR_CFG_LEVEL), \
60 INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \
61 GIC_INTR_CFG_LEVEL), \
62 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \
63 GIC_INTR_CFG_LEVEL), \
64 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
65 GIC_INTR_CFG_LEVEL)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000066
Soby Mathew1ced6b82017-06-12 12:37:10 +010067#if CSS_USE_SCMI_SDS_DRIVER
68/* Memory region for shared data storage */
69#define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE
70#define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */
Achin Gupta1fa7eb62015-11-03 14:18:34 +000071/*
Soby Mathew1ced6b82017-06-12 12:37:10 +010072 * The SCMI Channel is placed right after the SDS region
Soby Mathewea26bad2016-11-14 12:25:45 +000073 */
Soby Mathew1ced6b82017-06-12 12:37:10 +010074#define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX)
75#define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET
76
77/* Trusted mailbox base address common to all CSS */
78/* If SDS is present, then mailbox is at top of SRAM */
79#define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8)
Soby Mathewea26bad2016-11-14 12:25:45 +000080
Soby Mathew1ced6b82017-06-12 12:37:10 +010081/* Number of retries for SCP_RAM_READY flag */
82#define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */
83
84#else
Soby Mathewea26bad2016-11-14 12:25:45 +000085/*
Sandrine Bailleux761bba32015-04-29 13:02:46 +010086 * SCP <=> AP boot configuration
87 *
88 * The SCP/AP boot configuration is a 32-bit word located at a known offset from
Vikram Kanigiri72084192016-02-08 16:29:30 +000089 * the start of the Trusted SRAM.
Sandrine Bailleux761bba32015-04-29 13:02:46 +010090 *
91 * Note that the value stored at this address is only valid at boot time, before
Juan Castilloa72b6472015-12-10 15:49:17 +000092 * the SCP_BL2 image is transferred to SCP.
Sandrine Bailleux761bba32015-04-29 13:02:46 +010093 */
Vikram Kanigiri72084192016-02-08 16:29:30 +000094#define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE
Dan Handley9df48042015-03-19 18:58:55 +000095
Soby Mathew1ced6b82017-06-12 12:37:10 +010096/* Trusted mailbox base address common to all CSS */
97/* If SDS is not present, then the mailbox is at the bottom of SRAM */
98#define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE
99
100#endif /* CSS_USE_SCMI_SDS_DRIVER */
101
Dan Handley9df48042015-03-19 18:58:55 +0000102#define CSS_MAP_DEVICE MAP_REGION_FLAT( \
103 CSS_DEVICE_BASE, \
104 CSS_DEVICE_SIZE, \
105 MT_DEVICE | MT_RW | MT_SECURE)
106
Soby Mathewcbafd7a2016-11-14 12:44:32 +0000107#define CSS_MAP_NSRAM MAP_REGION_FLAT( \
108 NSRAM_BASE, \
109 NSRAM_SIZE, \
Chris Kay64491822018-05-10 14:43:28 +0100110 MT_DEVICE | MT_RW | MT_NS)
Soby Mathewcbafd7a2016-11-14 12:44:32 +0000111
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100112#if defined(IMAGE_BL2U)
113#define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \
114 SCP_BL2U_BASE, \
115 SCP_BL2U_LIMIT \
116 - SCP_BL2U_BASE,\
117 MT_RW_DATA | MT_SECURE)
118#endif
119
Vikram Kanigirif79d1502015-11-12 17:22:16 +0000120/* Platform ID address */
121#define SSC_VERSION_OFFSET 0x040
122
123#define SSC_VERSION_CONFIG_SHIFT 28
124#define SSC_VERSION_MAJOR_REV_SHIFT 24
125#define SSC_VERSION_MINOR_REV_SHIFT 20
126#define SSC_VERSION_DESIGNER_ID_SHIFT 12
127#define SSC_VERSION_PART_NUM_SHIFT 0x0
128#define SSC_VERSION_CONFIG_MASK 0xf
129#define SSC_VERSION_MAJOR_REV_MASK 0xf
130#define SSC_VERSION_MINOR_REV_MASK 0xf
131#define SSC_VERSION_DESIGNER_ID_MASK 0xff
132#define SSC_VERSION_PART_NUM_MASK 0xfff
133
Chandni Cherukuri346c7ca2018-09-16 21:05:49 +0530134#define SID_SYSTEM_ID_PART_NUM_MASK 0xfff
135
dp-armb71946b2017-02-08 12:16:42 +0000136/* SSC debug configuration registers */
137#define SSC_DBGCFG_SET 0x14
138#define SSC_DBGCFG_CLR 0x18
139
140#define SPIDEN_INT_CLR_SHIFT 6
141#define SPIDEN_SEL_SET_SHIFT 7
142
Julius Werner53456fc2019-07-09 13:49:11 -0700143#ifndef __ASSEMBLER__
Vikram Kanigirif79d1502015-11-12 17:22:16 +0000144
145/* SSC_VERSION related accessors */
146
147/* Returns the part number of the platform */
148#define GET_SSC_VERSION_PART_NUM(val) \
149 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \
150 SSC_VERSION_PART_NUM_MASK)
151
152/* Returns the configuration number of the platform */
153#define GET_SSC_VERSION_CONFIG(val) \
154 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \
155 SSC_VERSION_CONFIG_MASK)
156
Julius Werner53456fc2019-07-09 13:49:11 -0700157#endif /* __ASSEMBLER__ */
Dan Handley9df48042015-03-19 18:58:55 +0000158
159/*************************************************************************
160 * Required platform porting definitions common to all
161 * ARM Compute SubSystems (CSS)
162 ************************************************************************/
163
164/*
Vikram Kanigiri18a17312016-01-14 14:26:27 +0000165 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there
166 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE).
167 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load
168 * an SCP_BL2/SCP_BL2U image.
169 */
170#if CSS_LOAD_SCP_IMAGES
Soby Mathew2f6cac42017-06-13 18:00:53 +0100171
172#if ARM_BL31_IN_DRAM
173#error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config"
174#endif
175
Vikram Kanigiri18a17312016-01-14 14:26:27 +0000176/*
Juan Castilloa72b6472015-12-10 15:49:17 +0000177 * Load address of SCP_BL2 in CSS platform ports
Soby Mathew2f6cac42017-06-13 18:00:53 +0100178 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1
Soby Mathewaf14b462018-06-01 16:53:38 +0100179 * rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and
180 * BL31 is loaded over the top.
Dan Handley9df48042015-03-19 18:58:55 +0000181 */
Soby Mathewaf14b462018-06-01 16:53:38 +0100182#define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE)
183#define SCP_BL2_LIMIT BL2_BASE
Dan Handley9df48042015-03-19 18:58:55 +0000184
Soby Mathewaf14b462018-06-01 16:53:38 +0100185#define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE)
186#define SCP_BL2U_LIMIT BL2_BASE
Vikram Kanigiri18a17312016-01-14 14:26:27 +0000187#endif /* CSS_LOAD_SCP_IMAGES */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +0100188
Dan Handley9df48042015-03-19 18:58:55 +0000189/* Load address of Non-Secure Image for CSS platform ports */
Sandrine Bailleuxafa91db2019-01-31 15:01:32 +0100190#define PLAT_ARM_NS_IMAGE_BASE U(0xE0000000)
Dan Handley9df48042015-03-19 18:58:55 +0000191
192/* TZC related constants */
Soby Mathew9c708b52016-02-26 14:23:19 +0000193#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL
Vikram Kanigiria2cee032015-07-31 16:35:05 +0100194
Jeenu Viswambharan9cc4fc02016-08-04 09:43:15 +0100195/*
196 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP
197 * command
198 */
199#define CSS_CLUSTER_PWR_STATE_ON 0
200#define CSS_CLUSTER_PWR_STATE_OFF 3
201
202#define CSS_CPU_PWR_STATE_ON 1
203#define CSS_CPU_PWR_STATE_OFF 0
204#define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1)
Soby Mathewfeac8fc2015-09-29 15:47:16 +0100205
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000206#endif /* CSS_DEF_H */