Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved. |
Varun Wadekar | 5ee3abc | 2018-06-12 16:49:12 -0700 | [diff] [blame] | 3 | * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 6 | */ |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 7 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 8 | #include <asm_macros.S> |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 9 | #include <assert_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 10 | #include <common/bl_common.h> |
| 11 | #include <common/debug.h> |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 12 | #include <cortex_a57.h> |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 13 | #include <cpu_macros.S> |
| 14 | #include <plat_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 15 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 16 | /* --------------------------------------------- |
| 17 | * Disable L1 data cache and unified L2 cache |
| 18 | * --------------------------------------------- |
| 19 | */ |
| 20 | func cortex_a57_disable_dcache |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 21 | sysreg_bit_clear sctlr_el3, SCTLR_C_BIT |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 22 | isb |
| 23 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 24 | endfunc cortex_a57_disable_dcache |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 25 | |
| 26 | /* --------------------------------------------- |
| 27 | * Disable all types of L2 prefetches. |
| 28 | * --------------------------------------------- |
| 29 | */ |
| 30 | func cortex_a57_disable_l2_prefetch |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 31 | mrs x0, CORTEX_A57_ECTLR_EL1 |
| 32 | orr x0, x0, #CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT |
| 33 | mov x1, #CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK |
| 34 | orr x1, x1, #CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 35 | bic x0, x0, x1 |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 36 | msr CORTEX_A57_ECTLR_EL1, x0 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 37 | isb |
Soby Mathew | 1604fa0 | 2014-09-22 12:15:26 +0100 | [diff] [blame] | 38 | dsb ish |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 39 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 40 | endfunc cortex_a57_disable_l2_prefetch |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 41 | |
| 42 | /* --------------------------------------------- |
| 43 | * Disable intra-cluster coherency |
| 44 | * --------------------------------------------- |
| 45 | */ |
| 46 | func cortex_a57_disable_smp |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 47 | sysreg_bit_clear CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 48 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 49 | endfunc cortex_a57_disable_smp |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 50 | |
| 51 | /* --------------------------------------------- |
| 52 | * Disable debug interfaces |
| 53 | * --------------------------------------------- |
| 54 | */ |
| 55 | func cortex_a57_disable_ext_debug |
| 56 | mov x0, #1 |
| 57 | msr osdlr_el1, x0 |
| 58 | isb |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 59 | |
| 60 | apply_erratum cortex_a57, ERRATUM(817169), ERRATA_A57_817169 |
| 61 | |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 62 | dsb sy |
| 63 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 64 | endfunc cortex_a57_disable_ext_debug |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 65 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 66 | /* |
| 67 | * Disable the over-read from the LDNP/STNP instruction. The SDEN doesn't |
| 68 | * provide and erratum number, so assign it an obvious 1 |
| 69 | */ |
| 70 | workaround_reset_start cortex_a57, ERRATUM(1), A57_DISABLE_NON_TEMPORAL_HINT |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 71 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 72 | workaround_reset_end cortex_a57, ERRATUM(1) |
Boyan Karatotev | 219aa67 | 2023-04-04 11:59:12 +0100 | [diff] [blame] | 73 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 74 | check_erratum_ls cortex_a57, ERRATUM(1), CPU_REV(1, 2) |
Boyan Karatotev | 219aa67 | 2023-04-04 11:59:12 +0100 | [diff] [blame] | 75 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 76 | workaround_reset_start cortex_a57, ERRATUM(806969), ERRATA_A57_806969 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 77 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 78 | workaround_reset_end cortex_a57, ERRATUM(806969) |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 79 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 80 | check_erratum_ls cortex_a57, ERRATUM(806969), CPU_REV(0, 0) |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 81 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 82 | /* erratum always worked around, but report it correctly */ |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 83 | check_erratum_ls cortex_a57, ERRATUM(813419), CPU_REV(0, 0) |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 84 | add_erratum_entry cortex_a57, ERRATUM(813419), ERRATUM_ALWAYS_CHOSEN, NO_APPLY_AT_RESET |
Antonio Nino Diaz | 3f13c35 | 2017-02-24 11:39:22 +0000 | [diff] [blame] | 85 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 86 | workaround_reset_start cortex_a57, ERRATUM(813420), ERRATA_A57_813420 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 87 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 88 | workaround_reset_end cortex_a57, ERRATUM(813420) |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 89 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 90 | check_erratum_ls cortex_a57, ERRATUM(813420), CPU_REV(0, 0) |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 91 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 92 | workaround_reset_start cortex_a57, ERRATUM(814670), ERRATA_A57_814670 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 93 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_DMB_NULLIFICATION |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 94 | workaround_reset_end cortex_a57, ERRATUM(814670) |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 95 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 96 | check_erratum_ls cortex_a57, ERRATUM(814670), CPU_REV(0, 0) |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 97 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 98 | workaround_runtime_start cortex_a57, ERRATUM(817169), ERRATA_A57_817169, CORTEX_A57_MIDR |
| 99 | /* Invalidate any TLB address */ |
| 100 | mov x0, #0 |
| 101 | tlbi vae3, x0 |
| 102 | workaround_runtime_end cortex_a57, ERRATUM(817169), NO_ISB |
| 103 | |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 104 | check_erratum_ls cortex_a57, ERRATUM(817169), CPU_REV(0, 1) |
Ambroise Vincent | aa2c029 | 2019-02-21 16:35:49 +0000 | [diff] [blame] | 105 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 106 | workaround_reset_start cortex_a57, ERRATUM(826974), ERRATA_A57_826974 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 107 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 108 | workaround_reset_end cortex_a57, ERRATUM(826974) |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 109 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 110 | check_erratum_ls cortex_a57, ERRATUM(826974), CPU_REV(1, 1) |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 111 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 112 | workaround_reset_start cortex_a57, ERRATUM(826977), ERRATA_A57_826977 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 113 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 114 | workaround_reset_end cortex_a57, ERRATUM(826977) |
Sandrine Bailleux | adcbd55 | 2016-04-14 14:24:13 +0100 | [diff] [blame] | 115 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 116 | check_erratum_ls cortex_a57, ERRATUM(826977), CPU_REV(1, 1) |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 117 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 118 | workaround_reset_start cortex_a57, ERRATUM(828024), ERRATA_A57_828024 |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 119 | mrs x1, CORTEX_A57_CPUACTLR_EL1 |
Sandrine Bailleux | c11116f | 2016-04-14 14:04:48 +0100 | [diff] [blame] | 120 | /* |
| 121 | * Setting the relevant bits in CPUACTLR_EL1 has to be done in 2 |
| 122 | * instructions here because the resulting bitmask doesn't fit in a |
| 123 | * 16-bit value so it cannot be encoded in a single instruction. |
| 124 | */ |
Eleanor Bonnici | 41b61be | 2017-08-09 16:42:40 +0100 | [diff] [blame] | 125 | orr x1, x1, #CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA |
| 126 | orr x1, x1, #(CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING | \ |
| 127 | CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING) |
| 128 | msr CORTEX_A57_CPUACTLR_EL1, x1 |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 129 | workaround_reset_end cortex_a57, ERRATUM(828024) |
Sandrine Bailleux | a7e0c53 | 2016-04-14 13:32:31 +0100 | [diff] [blame] | 130 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 131 | check_erratum_ls cortex_a57, ERRATUM(828024), CPU_REV(1, 1) |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 132 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 133 | workaround_reset_start cortex_a57, ERRATUM(829520), ERRATA_A57_829520 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 134 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 135 | workaround_reset_end cortex_a57, ERRATUM(829520) |
Sandrine Bailleux | 48cbe85 | 2016-04-14 14:18:07 +0100 | [diff] [blame] | 136 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 137 | check_erratum_ls cortex_a57, ERRATUM(829520), CPU_REV(1, 2) |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 138 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 139 | workaround_reset_start cortex_a57, ERRATUM(833471), ERRATA_A57_833471 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 140 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 141 | workaround_reset_end cortex_a57, ERRATUM(833471) |
Sandrine Bailleux | 143ef1a | 2016-04-21 11:10:52 +0100 | [diff] [blame] | 142 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 143 | check_erratum_ls cortex_a57, ERRATUM(833471), CPU_REV(1, 2) |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 144 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 145 | workaround_reset_start cortex_a57, ERRATUM(859972), ERRATA_A57_859972 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 146 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 147 | workaround_reset_end cortex_a57, ERRATUM(859972) |
Boyan Karatotev | 219aa67 | 2023-04-04 11:59:12 +0100 | [diff] [blame] | 148 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 149 | check_erratum_ls cortex_a57, ERRATUM(859972), CPU_REV(1, 3) |
Soby Mathew | 802f865 | 2014-08-14 16:19:29 +0100 | [diff] [blame] | 150 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 151 | check_erratum_chosen cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537 |
| 152 | /* erratum has no workaround in the cpu. Generic code must take care */ |
| 153 | add_erratum_entry cortex_a57, ERRATUM(1319537), ERRATA_A57_1319537, NO_APPLY_AT_RESET |
Ambroise Vincent | 1b0db76 | 2019-02-21 16:35:07 +0000 | [diff] [blame] | 154 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 155 | workaround_reset_start cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
| 156 | #if IMAGE_BL31 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 157 | override_vector_table wa_cve_2017_5715_mmu_vbar |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 158 | #endif |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 159 | workaround_reset_end cortex_a57, CVE(2017, 5715) |
| 160 | |
| 161 | check_erratum_chosen cortex_a57, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
Dimitris Papastamos | 446f7f1 | 2017-11-30 14:53:53 +0000 | [diff] [blame] | 162 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 163 | workaround_reset_start cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 164 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 165 | isb |
| 166 | dsb sy |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 167 | workaround_reset_end cortex_a57, CVE(2018, 3639) |
| 168 | |
| 169 | check_erratum_chosen cortex_a57, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
| 170 | |
| 171 | workaround_reset_start cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 172 | #if IMAGE_BL31 |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 173 | override_vector_table wa_cve_2017_5715_mmu_vbar |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 174 | #endif |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 175 | workaround_reset_end cortex_a57, CVE(2022, 23960) |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 176 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 177 | check_erratum_chosen cortex_a57, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 178 | |
| 179 | cpu_reset_func_start cortex_a57 |
Varun Wadekar | 5ee3abc | 2018-06-12 16:49:12 -0700 | [diff] [blame] | 180 | #if A57_ENABLE_NONCACHEABLE_LOAD_FWD |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 181 | /* Enable higher performance non-cacheable load forwarding */ |
| 182 | sysreg_bit_set CORTEX_A57_CPUACTLR_EL1, CORTEX_A57_CPUACTLR_EL1_EN_NC_LOAD_FWD |
Varun Wadekar | 5ee3abc | 2018-06-12 16:49:12 -0700 | [diff] [blame] | 183 | #endif |
Boyan Karatotev | c88e891 | 2023-04-05 16:22:20 +0100 | [diff] [blame] | 184 | /* Enable the SMP bit. */ |
| 185 | sysreg_bit_set CORTEX_A57_ECTLR_EL1, CORTEX_A57_ECTLR_SMP_BIT |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 186 | cpu_reset_func_end cortex_a57 |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 187 | |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 188 | func check_smccc_arch_workaround_3 |
| 189 | mov x0, #ERRATA_APPLIES |
| 190 | ret |
| 191 | endfunc check_smccc_arch_workaround_3 |
| 192 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 193 | /* ---------------------------------------------------- |
| 194 | * The CPU Ops core power down function for Cortex-A57. |
| 195 | * ---------------------------------------------------- |
| 196 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 197 | func cortex_a57_core_pwr_dwn |
| 198 | mov x18, x30 |
| 199 | |
| 200 | /* --------------------------------------------- |
| 201 | * Turn off caches. |
| 202 | * --------------------------------------------- |
| 203 | */ |
| 204 | bl cortex_a57_disable_dcache |
| 205 | |
| 206 | /* --------------------------------------------- |
| 207 | * Disable the L2 prefetches. |
| 208 | * --------------------------------------------- |
| 209 | */ |
| 210 | bl cortex_a57_disable_l2_prefetch |
| 211 | |
| 212 | /* --------------------------------------------- |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 213 | * Flush L1 caches. |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 214 | * --------------------------------------------- |
| 215 | */ |
| 216 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 217 | bl dcsw_op_level1 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 218 | |
| 219 | /* --------------------------------------------- |
| 220 | * Come out of intra cluster coherency |
| 221 | * --------------------------------------------- |
| 222 | */ |
| 223 | bl cortex_a57_disable_smp |
| 224 | |
| 225 | /* --------------------------------------------- |
| 226 | * Force the debug interfaces to be quiescent |
| 227 | * --------------------------------------------- |
| 228 | */ |
| 229 | mov x30, x18 |
| 230 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 231 | endfunc cortex_a57_core_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 232 | |
Soby Mathew | c088433 | 2014-09-22 12:11:36 +0100 | [diff] [blame] | 233 | /* ------------------------------------------------------- |
| 234 | * The CPU Ops cluster power down function for Cortex-A57. |
| 235 | * ------------------------------------------------------- |
| 236 | */ |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 237 | func cortex_a57_cluster_pwr_dwn |
| 238 | mov x18, x30 |
| 239 | |
| 240 | /* --------------------------------------------- |
| 241 | * Turn off caches. |
| 242 | * --------------------------------------------- |
| 243 | */ |
| 244 | bl cortex_a57_disable_dcache |
| 245 | |
| 246 | /* --------------------------------------------- |
| 247 | * Disable the L2 prefetches. |
| 248 | * --------------------------------------------- |
| 249 | */ |
| 250 | bl cortex_a57_disable_l2_prefetch |
| 251 | |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 252 | #if !SKIP_A57_L1_FLUSH_PWR_DWN |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 253 | /* ------------------------------------------------- |
| 254 | * Flush the L1 caches. |
| 255 | * ------------------------------------------------- |
| 256 | */ |
| 257 | mov x0, #DCCISW |
| 258 | bl dcsw_op_level1 |
Soby Mathew | 937488b | 2014-09-22 14:13:34 +0100 | [diff] [blame] | 259 | #endif |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 260 | /* --------------------------------------------- |
| 261 | * Disable the optional ACP. |
| 262 | * --------------------------------------------- |
| 263 | */ |
| 264 | bl plat_disable_acp |
| 265 | |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 266 | /* ------------------------------------------------- |
| 267 | * Flush the L2 caches. |
| 268 | * ------------------------------------------------- |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 269 | */ |
| 270 | mov x0, #DCCISW |
Soby Mathew | 42aa5eb | 2014-09-02 10:47:33 +0100 | [diff] [blame] | 271 | bl dcsw_op_level2 |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 272 | |
| 273 | /* --------------------------------------------- |
| 274 | * Come out of intra cluster coherency |
| 275 | * --------------------------------------------- |
| 276 | */ |
| 277 | bl cortex_a57_disable_smp |
| 278 | |
| 279 | /* --------------------------------------------- |
| 280 | * Force the debug interfaces to be quiescent |
| 281 | * --------------------------------------------- |
| 282 | */ |
| 283 | mov x30, x18 |
| 284 | b cortex_a57_disable_ext_debug |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 285 | endfunc cortex_a57_cluster_pwr_dwn |
Soby Mathew | 8e2f287 | 2014-08-14 12:49:05 +0100 | [diff] [blame] | 286 | |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 287 | errata_report_shim cortex_a57 |
Jeenu Viswambharan | d5ec367 | 2017-01-03 11:01:51 +0000 | [diff] [blame] | 288 | |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 289 | /* --------------------------------------------- |
| 290 | * This function provides cortex_a57 specific |
| 291 | * register information for crash reporting. |
| 292 | * It needs to return with x6 pointing to |
| 293 | * a list of register names in ascii and |
| 294 | * x8 - x15 having values of registers to be |
| 295 | * reported. |
| 296 | * --------------------------------------------- |
| 297 | */ |
| 298 | .section .rodata.cortex_a57_regs, "aS" |
| 299 | cortex_a57_regs: /* The ascii list of register names to be reported */ |
Naga Sureshkumar Relli | 6a72a91 | 2016-07-01 12:52:41 +0530 | [diff] [blame] | 300 | .asciz "cpuectlr_el1", "cpumerrsr_el1", "l2merrsr_el1", "" |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 301 | |
| 302 | func cortex_a57_cpu_reg_dump |
| 303 | adr x6, cortex_a57_regs |
Varun Wadekar | 1384a16 | 2017-06-05 14:54:46 -0700 | [diff] [blame] | 304 | mrs x8, CORTEX_A57_ECTLR_EL1 |
| 305 | mrs x9, CORTEX_A57_MERRSR_EL1 |
| 306 | mrs x10, CORTEX_A57_L2MERRSR_EL1 |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 307 | ret |
Kévin Petit | a877c25 | 2015-03-24 14:03:57 +0000 | [diff] [blame] | 308 | endfunc cortex_a57_cpu_reg_dump |
Soby Mathew | 38b4bc9 | 2014-08-14 13:36:41 +0100 | [diff] [blame] | 309 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 310 | declare_cpu_ops_wa cortex_a57, CORTEX_A57_MIDR, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 311 | cortex_a57_reset_func, \ |
Boyan Karatotev | d2ae7c9 | 2023-04-05 10:49:37 +0100 | [diff] [blame] | 312 | check_erratum_cortex_a57_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 313 | CPU_NO_EXTRA2_FUNC, \ |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 314 | check_smccc_arch_workaround_3, \ |
Jeenu Viswambharan | ee5eb80 | 2016-11-18 12:58:28 +0000 | [diff] [blame] | 315 | cortex_a57_core_pwr_dwn, \ |
| 316 | cortex_a57_cluster_pwr_dwn |