David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 1 | /* |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 2 | * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <common/bl_common.h> |
Isla Mitchell | 9930501 | 2017-07-11 14:54:08 +0100 | [diff] [blame] | 10 | #include <cortex_a55.h> |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
John Tsichritzis | fe6df39 | 2019-03-19 17:20:52 +0000 | [diff] [blame] | 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Cortex-A55 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
Saurabh Gorecha | b849301 | 2022-04-05 00:11:52 +0530 | [diff] [blame] | 19 | .globl cortex_a55_reset_func |
| 20 | .globl cortex_a55_core_pwr_dwn |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 21 | |
| 22 | /* ERRATA_DSU_798953: |
| 23 | * The errata is defined in dsu_helpers.S but applies to cortex_a55 |
| 24 | * as well. Henceforth creating symbolic names to the already existing errata |
| 25 | * workaround functions to get them registered under the Errata Framework. |
| 26 | */ |
| 27 | .equ check_erratum_cortex_a55_798953, check_errata_dsu_798953 |
| 28 | .equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa |
| 29 | add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET |
| 30 | |
| 31 | /* ERRATA_DSU_936184: |
| 32 | * The errata is defined in dsu_helpers.S but applies to cortex_a55 |
| 33 | * as well. Henceforth creating symbolic names to the already existing errata |
| 34 | * workaround functions to get them registered under the Errata Framework. |
| 35 | */ |
| 36 | .equ check_erratum_cortex_a55_936184, check_errata_dsu_936184 |
| 37 | .equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa |
| 38 | add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET |
| 39 | |
| 40 | workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277 |
Govindraj Raja | 0a0b99a | 2023-06-15 15:47:15 -0500 | [diff] [blame] | 41 | sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 42 | workaround_reset_end cortex_a55, ERRATUM(768277) |
Ambroise Vincent | 7927fa0 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 43 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 44 | check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0) |
Ambroise Vincent | 7927fa0 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 45 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 46 | workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703 |
Govindraj Raja | 0a0b99a | 2023-06-15 15:47:15 -0500 | [diff] [blame] | 47 | sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL |
| 48 | sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 49 | workaround_reset_end cortex_a55, ERRATUM(778703) |
Ambroise Vincent | 6f31960 | 2019-02-21 16:25:37 +0000 | [diff] [blame] | 50 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 51 | check_erratum_custom_start cortex_a55, ERRATUM(778703) |
Ambroise Vincent | 6f31960 | 2019-02-21 16:25:37 +0000 | [diff] [blame] | 52 | mov x16, x30 |
| 53 | mov x1, #0x00 |
| 54 | bl cpu_rev_var_ls |
| 55 | /* |
| 56 | * Check that no private L2 cache is configured |
| 57 | */ |
| 58 | mrs x1, CORTEX_A55_CLIDR_EL1 |
| 59 | and x1, x1, CORTEX_A55_CLIDR_EL1_CTYPE3 |
| 60 | cmp x1, #0 |
| 61 | mov x2, #ERRATA_NOT_APPLIES |
| 62 | csel x0, x0, x2, eq |
| 63 | ret x16 |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 64 | check_erratum_custom_end cortex_a55, ERRATUM(778703) |
Ambroise Vincent | 6f31960 | 2019-02-21 16:25:37 +0000 | [diff] [blame] | 65 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 66 | workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797 |
Govindraj Raja | 0a0b99a | 2023-06-15 15:47:15 -0500 | [diff] [blame] | 67 | sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 68 | workaround_reset_end cortex_a55, ERRATUM(798797) |
Ambroise Vincent | 6a77f05 | 2019-02-21 16:27:34 +0000 | [diff] [blame] | 69 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 70 | check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0) |
Ambroise Vincent | 6a77f05 | 2019-02-21 16:27:34 +0000 | [diff] [blame] | 71 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 72 | workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532 |
Govindraj Raja | 0a0b99a | 2023-06-15 15:47:15 -0500 | [diff] [blame] | 73 | sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 74 | workaround_reset_end cortex_a55, ERRATUM(846532) |
Ambroise Vincent | dd961f7 | 2019-02-21 16:29:16 +0000 | [diff] [blame] | 75 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 76 | check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1) |
Ambroise Vincent | dd961f7 | 2019-02-21 16:29:16 +0000 | [diff] [blame] | 77 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 78 | workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758 |
Govindraj Raja | 0a0b99a | 2023-06-15 15:47:15 -0500 | [diff] [blame] | 79 | sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 80 | workaround_reset_end cortex_a55, ERRATUM(903758) |
Ambroise Vincent | a1d6446 | 2019-02-21 16:29:50 +0000 | [diff] [blame] | 81 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 82 | check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1) |
Ambroise Vincent | a1d6446 | 2019-02-21 16:29:50 +0000 | [diff] [blame] | 83 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 84 | workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012 |
Ambroise Vincent | b72fe7a | 2019-05-28 09:52:48 +0100 | [diff] [blame] | 85 | mov x0, #0x0020 |
| 86 | movk x0, #0x0850, lsl #16 |
| 87 | msr CPUPOR_EL3, x0 |
| 88 | mov x0, #0x0000 |
| 89 | movk x0, #0x1FF0, lsl #16 |
| 90 | movk x0, #0x2, lsl #32 |
| 91 | msr CPUPMR_EL3, x0 |
| 92 | mov x0, #0x03fd |
| 93 | movk x0, #0x0110, lsl #16 |
| 94 | msr CPUPCR_EL3, x0 |
| 95 | mov x0, #0x1 |
| 96 | msr CPUPSELR_EL3, x0 |
| 97 | mov x0, #0x0040 |
| 98 | movk x0, #0x08D0, lsl #16 |
| 99 | msr CPUPOR_EL3, x0 |
| 100 | mov x0, #0x0040 |
| 101 | movk x0, #0x1FF0, lsl #16 |
| 102 | movk x0, #0x2, lsl #32 |
| 103 | msr CPUPMR_EL3, x0 |
| 104 | mov x0, #0x03fd |
| 105 | movk x0, #0x0110, lsl #16 |
| 106 | msr CPUPCR_EL3, x0 |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 107 | workaround_reset_end cortex_a55, ERRATUM(1221012) |
Ambroise Vincent | b72fe7a | 2019-05-28 09:52:48 +0100 | [diff] [blame] | 108 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 109 | check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0) |
Manish V Badarkhe | 7672edf | 2020-08-03 18:43:14 +0100 | [diff] [blame] | 110 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 111 | check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923 |
Ambroise Vincent | 7927fa0 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 112 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 113 | /* erratum has no workaround in the cpu. Generic code must take care */ |
| 114 | add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET |
Louis Mayencourt | 4498b15 | 2019-04-09 16:29:01 +0100 | [diff] [blame] | 115 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 116 | cpu_reset_func_start cortex_a55 |
| 117 | cpu_reset_func_end cortex_a55 |
Ambroise Vincent | 7927fa0 | 2019-02-21 16:20:43 +0000 | [diff] [blame] | 118 | |
Govindraj Raja | 5a8a106 | 2023-06-15 15:44:42 -0500 | [diff] [blame] | 119 | errata_report_shim cortex_a55 |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 120 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 121 | /* --------------------------------------------- |
| 122 | * HW will do the cache maintenance while powering down |
| 123 | * --------------------------------------------- |
| 124 | */ |
| 125 | func cortex_a55_core_pwr_dwn |
Govindraj Raja | 0a0b99a | 2023-06-15 15:47:15 -0500 | [diff] [blame] | 126 | sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 127 | isb |
| 128 | ret |
| 129 | endfunc cortex_a55_core_pwr_dwn |
| 130 | |
| 131 | /* --------------------------------------------- |
| 132 | * This function provides cortex_a55 specific |
| 133 | * register information for crash reporting. |
| 134 | * It needs to return with x6 pointing to |
| 135 | * a list of register names in ascii and |
| 136 | * x8 - x15 having values of registers to be |
| 137 | * reported. |
| 138 | * --------------------------------------------- |
| 139 | */ |
| 140 | .section .rodata.cortex_a55_regs, "aS" |
| 141 | cortex_a55_regs: /* The ascii list of register names to be reported */ |
| 142 | .asciz "cpuectlr_el1", "" |
| 143 | |
| 144 | func cortex_a55_cpu_reg_dump |
| 145 | adr x6, cortex_a55_regs |
| 146 | mrs x8, CORTEX_A55_CPUECTLR_EL1 |
| 147 | ret |
| 148 | endfunc cortex_a55_cpu_reg_dump |
| 149 | |
| 150 | declare_cpu_ops cortex_a55, CORTEX_A55_MIDR, \ |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 151 | cortex_a55_reset_func, \ |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 152 | cortex_a55_core_pwr_dwn |