DSU: Implement workaround for errata 798953
Under certain near idle conditions, DSU may miss response transfers on
the ACE master or Peripheral port, leading to deadlock. This workaround
disables high-level clock gating of the DSU to prevent this.
Change-Id: I820911d61570bacb38dd325b3519bc8d12caa14b
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 1da80ef..b9a3f36 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -173,6 +173,10 @@
func cortex_a55_reset_func
mov x19, x30
+#if ERRATA_DSU_798953
+ bl errata_dsu_798953_wa
+#endif
+
#if ERRATA_DSU_936184
bl errata_dsu_936184_wa
#endif
@@ -237,6 +241,7 @@
* Report all errata. The revision variant information is at x8, where
* "report_errata" is expecting it and it doesn't corrupt it.
*/
+ report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953
report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
report_errata ERRATA_A55_768277, cortex_a55, 768277
report_errata ERRATA_A55_778703, cortex_a55, 778703