Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch_helpers.h> |
| 32 | #include <assert.h> |
| 33 | #include <bl_common.h> |
| 34 | #include <cci400.h> |
| 35 | #include <console.h> |
| 36 | #include <debug.h> |
| 37 | #include <mmio.h> |
| 38 | #include <platform.h> |
| 39 | #include <platform_def.h> |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 40 | #include "../../bl1/bl1_private.h" |
| 41 | #include "juno_def.h" |
| 42 | #include "juno_private.h" |
| 43 | |
| 44 | /******************************************************************************* |
| 45 | * Declarations of linker defined symbols which will help us find the layout |
| 46 | * of trusted RAM |
| 47 | ******************************************************************************/ |
| 48 | extern unsigned long __COHERENT_RAM_START__; |
| 49 | extern unsigned long __COHERENT_RAM_END__; |
| 50 | |
| 51 | /* |
| 52 | * The next 2 constants identify the extents of the coherent memory region. |
| 53 | * These addresses are used by the MMU setup code and therefore they must be |
| 54 | * page-aligned. It is the responsibility of the linker script to ensure that |
| 55 | * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to |
| 56 | * page-aligned addresses. |
| 57 | */ |
| 58 | #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) |
| 59 | #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) |
| 60 | |
| 61 | /* Data structure which holds the extents of the trusted RAM for BL1 */ |
| 62 | static meminfo_t bl1_tzram_layout; |
| 63 | |
| 64 | meminfo_t *bl1_plat_sec_mem_layout(void) |
| 65 | { |
| 66 | return &bl1_tzram_layout; |
| 67 | } |
| 68 | |
| 69 | /******************************************************************************* |
| 70 | * Perform any BL1 specific platform actions. |
| 71 | ******************************************************************************/ |
| 72 | void bl1_early_platform_setup(void) |
| 73 | { |
| 74 | const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE; |
| 75 | |
| 76 | /* Initialize the console to provide early debug support */ |
Soby Mathew | f797cea | 2014-08-21 15:20:27 +0100 | [diff] [blame] | 77 | console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE); |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 78 | |
| 79 | /* |
| 80 | * Enable CCI-400 for this cluster. No need for locks as no other cpu is |
| 81 | * active at the moment |
| 82 | */ |
| 83 | cci_init(CCI400_BASE, |
| 84 | CCI400_SL_IFACE3_CLUSTER_IX, |
| 85 | CCI400_SL_IFACE4_CLUSTER_IX); |
| 86 | cci_enable_cluster_coherency(read_mpidr()); |
| 87 | |
| 88 | /* Allow BL1 to see the whole Trusted RAM */ |
| 89 | bl1_tzram_layout.total_base = TZRAM_BASE; |
| 90 | bl1_tzram_layout.total_size = TZRAM_SIZE; |
| 91 | |
| 92 | /* Calculate how much RAM BL1 is using and how much remains free */ |
| 93 | bl1_tzram_layout.free_base = TZRAM_BASE; |
| 94 | bl1_tzram_layout.free_size = TZRAM_SIZE; |
| 95 | reserve_mem(&bl1_tzram_layout.free_base, |
| 96 | &bl1_tzram_layout.free_size, |
| 97 | BL1_RAM_BASE, |
| 98 | bl1_size); |
| 99 | |
| 100 | INFO("BL1: 0x%lx - 0x%lx [size = %u]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, |
| 101 | bl1_size); |
| 102 | } |
| 103 | |
| 104 | |
| 105 | /* |
| 106 | * Address of slave 'n' security setting in the NIC-400 address region |
| 107 | * control |
| 108 | * TODO: Ideally this macro should be moved in a "nic-400.h" header file but |
| 109 | * it would be the only thing in there so it's not worth it at the moment. |
| 110 | */ |
| 111 | #define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4) |
| 112 | |
| 113 | static void init_nic400(void) |
| 114 | { |
| 115 | /* |
| 116 | * NIC-400 Access Control Initialization |
| 117 | * |
| 118 | * Define access privileges by setting each corresponding bit to: |
| 119 | * 0 = Secure access only |
| 120 | * 1 = Non-secure access allowed |
| 121 | */ |
| 122 | |
| 123 | /* |
| 124 | * Allow non-secure access to some SOC regions, excluding UART1, which |
| 125 | * remains secure. |
| 126 | * Note: This is the NIC-400 device on the SOC |
| 127 | */ |
| 128 | mmio_write_32(SOC_NIC400_BASE + |
| 129 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_EHCI), ~0); |
| 130 | mmio_write_32(SOC_NIC400_BASE + |
| 131 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_TLX_MASTER), ~0); |
| 132 | mmio_write_32(SOC_NIC400_BASE + |
| 133 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_OHCI), ~0); |
| 134 | mmio_write_32(SOC_NIC400_BASE + |
| 135 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_PL354_SMC), ~0); |
| 136 | mmio_write_32(SOC_NIC400_BASE + |
| 137 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_APB4_BRIDGE), ~0); |
| 138 | mmio_write_32(SOC_NIC400_BASE + |
| 139 | NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_BOOTSEC_BRIDGE), |
| 140 | ~SOC_NIC400_BOOTSEC_BRIDGE_UART1); |
| 141 | |
| 142 | /* |
| 143 | * Allow non-secure access to some CSS regions. |
| 144 | * Note: This is the NIC-400 device on the CSS |
| 145 | */ |
| 146 | mmio_write_32(CSS_NIC400_BASE + |
| 147 | NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE), |
| 148 | ~0); |
| 149 | } |
| 150 | |
| 151 | |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 152 | #define PCIE_SECURE_REG 0x3000 |
| 153 | #define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */ |
| 154 | |
| 155 | static void init_pcie(void) |
| 156 | { |
| 157 | /* |
| 158 | * PCIE Root Complex Security settings to enable non-secure |
| 159 | * access to config registers. |
| 160 | */ |
| 161 | mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK); |
| 162 | } |
| 163 | |
| 164 | |
| 165 | /******************************************************************************* |
| 166 | * Function which will perform any remaining platform-specific setup that can |
| 167 | * occur after the MMU and data cache have been enabled. |
| 168 | ******************************************************************************/ |
| 169 | void bl1_platform_setup(void) |
| 170 | { |
| 171 | init_nic400(); |
Sandrine Bailleux | 798140d | 2014-07-17 16:06:39 +0100 | [diff] [blame] | 172 | init_pcie(); |
| 173 | |
| 174 | /* Initialise the IO layer and register platform IO devices */ |
| 175 | io_setup(); |
| 176 | |
| 177 | /* Enable and initialize the System level generic timer */ |
| 178 | mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN); |
| 179 | } |
| 180 | |
| 181 | |
| 182 | /******************************************************************************* |
| 183 | * Perform the very early platform specific architecture setup here. At the |
| 184 | * moment this only does basic initialization. Later architectural setup |
| 185 | * (bl1_arch_setup()) does not do anything platform specific. |
| 186 | ******************************************************************************/ |
| 187 | void bl1_plat_arch_setup(void) |
| 188 | { |
| 189 | configure_mmu_el3(bl1_tzram_layout.total_base, |
| 190 | bl1_tzram_layout.total_size, |
| 191 | TZROM_BASE, |
| 192 | TZROM_BASE + TZROM_SIZE, |
| 193 | BL1_COHERENT_RAM_BASE, |
| 194 | BL1_COHERENT_RAM_LIMIT); |
| 195 | } |
| 196 | |
| 197 | /******************************************************************************* |
| 198 | * Before calling this function BL2 is loaded in memory and its entrypoint |
| 199 | * is set by load_image. This is a placeholder for the platform to change |
| 200 | * the entrypoint of BL2 and set SPSR and security state. |
| 201 | * On Juno we are only setting the security state, entrypoint |
| 202 | ******************************************************************************/ |
| 203 | void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image, |
| 204 | entry_point_info_t *bl2_ep) |
| 205 | { |
| 206 | SET_SECURITY_STATE(bl2_ep->h.attr, SECURE); |
| 207 | bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); |
| 208 | } |