blob: 5804682c42c0db48c831517df4738d6ee23273f7 [file] [log] [blame]
Sandrine Bailleux798140d2014-07-17 16:06:39 +01001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch_helpers.h>
32#include <assert.h>
33#include <bl_common.h>
34#include <cci400.h>
35#include <console.h>
36#include <debug.h>
37#include <mmio.h>
38#include <platform.h>
39#include <platform_def.h>
40#include <tzc400.h>
41#include "../../bl1/bl1_private.h"
42#include "juno_def.h"
43#include "juno_private.h"
44
45/*******************************************************************************
46 * Declarations of linker defined symbols which will help us find the layout
47 * of trusted RAM
48 ******************************************************************************/
49extern unsigned long __COHERENT_RAM_START__;
50extern unsigned long __COHERENT_RAM_END__;
51
52/*
53 * The next 2 constants identify the extents of the coherent memory region.
54 * These addresses are used by the MMU setup code and therefore they must be
55 * page-aligned. It is the responsibility of the linker script to ensure that
56 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
57 * page-aligned addresses.
58 */
59#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
60#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
61
62/* Data structure which holds the extents of the trusted RAM for BL1 */
63static meminfo_t bl1_tzram_layout;
64
65meminfo_t *bl1_plat_sec_mem_layout(void)
66{
67 return &bl1_tzram_layout;
68}
69
70/*******************************************************************************
71 * Perform any BL1 specific platform actions.
72 ******************************************************************************/
73void bl1_early_platform_setup(void)
74{
75 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
76
77 /* Initialize the console to provide early debug support */
Soby Mathewf797cea2014-08-21 15:20:27 +010078 console_init(PL011_UART2_BASE, PL011_UART2_CLK_IN_HZ, PL011_BAUDRATE);
Sandrine Bailleux798140d2014-07-17 16:06:39 +010079
80 /*
81 * Enable CCI-400 for this cluster. No need for locks as no other cpu is
82 * active at the moment
83 */
84 cci_init(CCI400_BASE,
85 CCI400_SL_IFACE3_CLUSTER_IX,
86 CCI400_SL_IFACE4_CLUSTER_IX);
87 cci_enable_cluster_coherency(read_mpidr());
88
89 /* Allow BL1 to see the whole Trusted RAM */
90 bl1_tzram_layout.total_base = TZRAM_BASE;
91 bl1_tzram_layout.total_size = TZRAM_SIZE;
92
93 /* Calculate how much RAM BL1 is using and how much remains free */
94 bl1_tzram_layout.free_base = TZRAM_BASE;
95 bl1_tzram_layout.free_size = TZRAM_SIZE;
96 reserve_mem(&bl1_tzram_layout.free_base,
97 &bl1_tzram_layout.free_size,
98 BL1_RAM_BASE,
99 bl1_size);
100
101 INFO("BL1: 0x%lx - 0x%lx [size = %u]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
102 bl1_size);
103}
104
105
106/*
107 * Address of slave 'n' security setting in the NIC-400 address region
108 * control
109 * TODO: Ideally this macro should be moved in a "nic-400.h" header file but
110 * it would be the only thing in there so it's not worth it at the moment.
111 */
112#define NIC400_ADDR_CTRL_SECURITY_REG(n) (0x8 + (n) * 4)
113
114static void init_nic400(void)
115{
116 /*
117 * NIC-400 Access Control Initialization
118 *
119 * Define access privileges by setting each corresponding bit to:
120 * 0 = Secure access only
121 * 1 = Non-secure access allowed
122 */
123
124 /*
125 * Allow non-secure access to some SOC regions, excluding UART1, which
126 * remains secure.
127 * Note: This is the NIC-400 device on the SOC
128 */
129 mmio_write_32(SOC_NIC400_BASE +
130 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_EHCI), ~0);
131 mmio_write_32(SOC_NIC400_BASE +
132 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_TLX_MASTER), ~0);
133 mmio_write_32(SOC_NIC400_BASE +
134 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_USB_OHCI), ~0);
135 mmio_write_32(SOC_NIC400_BASE +
136 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_PL354_SMC), ~0);
137 mmio_write_32(SOC_NIC400_BASE +
138 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_APB4_BRIDGE), ~0);
139 mmio_write_32(SOC_NIC400_BASE +
140 NIC400_ADDR_CTRL_SECURITY_REG(SOC_NIC400_BOOTSEC_BRIDGE),
141 ~SOC_NIC400_BOOTSEC_BRIDGE_UART1);
142
143 /*
144 * Allow non-secure access to some CSS regions.
145 * Note: This is the NIC-400 device on the CSS
146 */
147 mmio_write_32(CSS_NIC400_BASE +
148 NIC400_ADDR_CTRL_SECURITY_REG(CSS_NIC400_SLAVE_BOOTSECURE),
149 ~0);
150}
151
152
153static void init_tzc400(void)
154{
155 /* Enable all filter units available */
156 mmio_write_32(TZC400_BASE + GATE_KEEPER_OFF, 0x0000000f);
157
158 /*
159 * Secure read and write are enabled for region 0, and the background
160 * region (region 0) is enabled for all four filter units
161 */
162 mmio_write_32(TZC400_BASE + REGION_ATTRIBUTES_OFF, 0xc0000000);
163
164 /*
165 * Enable Non-secure read/write accesses for the Soc Devices from the
166 * Non-Secure World
167 */
168 mmio_write_32(TZC400_BASE + REGION_ID_ACCESS_OFF,
169 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) |
170 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) |
171 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) |
172 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) |
173 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) |
174 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) |
175 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) |
176 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) |
177 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) |
178 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_SCP) |
179 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)
180 );
181}
182
183#define PCIE_SECURE_REG 0x3000
184#define PCIE_SEC_ACCESS_MASK ((1 << 0) | (1 << 1)) /* REG and MEM access bits */
185
186static void init_pcie(void)
187{
188 /*
189 * PCIE Root Complex Security settings to enable non-secure
190 * access to config registers.
191 */
192 mmio_write_32(PCIE_CONTROL_BASE + PCIE_SECURE_REG, PCIE_SEC_ACCESS_MASK);
193}
194
195
196/*******************************************************************************
197 * Function which will perform any remaining platform-specific setup that can
198 * occur after the MMU and data cache have been enabled.
199 ******************************************************************************/
200void bl1_platform_setup(void)
201{
202 init_nic400();
203 init_tzc400();
204 init_pcie();
205
206 /* Initialise the IO layer and register platform IO devices */
207 io_setup();
208
209 /* Enable and initialize the System level generic timer */
210 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
211}
212
213
214/*******************************************************************************
215 * Perform the very early platform specific architecture setup here. At the
216 * moment this only does basic initialization. Later architectural setup
217 * (bl1_arch_setup()) does not do anything platform specific.
218 ******************************************************************************/
219void bl1_plat_arch_setup(void)
220{
221 configure_mmu_el3(bl1_tzram_layout.total_base,
222 bl1_tzram_layout.total_size,
223 TZROM_BASE,
224 TZROM_BASE + TZROM_SIZE,
225 BL1_COHERENT_RAM_BASE,
226 BL1_COHERENT_RAM_LIMIT);
227}
228
229/*******************************************************************************
230 * Before calling this function BL2 is loaded in memory and its entrypoint
231 * is set by load_image. This is a placeholder for the platform to change
232 * the entrypoint of BL2 and set SPSR and security state.
233 * On Juno we are only setting the security state, entrypoint
234 ******************************************************************************/
235void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
236 entry_point_info_t *bl2_ep)
237{
238 SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
239 bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
240}