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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handleyed6ff952014-05-14 17:44:19 +01007#include <platform_def.h>
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +00008#include <xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000012ENTRY(bl31_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
14
15MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010016 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010017}
18
Caesar Wangd90f43e2016-10-11 09:36:00 +080019#ifdef PLAT_EXTRA_LD_SCRIPT
20#include <plat.ld.S>
21#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010022
23SECTIONS
24{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000025 . = BL31_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000026 ASSERT(. == ALIGN(PAGE_SIZE),
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000027 "BL31_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010028
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010029#if SEPARATE_CODE_AND_RODATA
30 .text . : {
31 __TEXT_START__ = .;
32 *bl31_entrypoint.o(.text*)
33 *(.text*)
34 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010035 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010036 __TEXT_END__ = .;
37 } >RAM
38
39 .rodata . : {
40 __RODATA_START__ = .;
41 *(.rodata*)
42
43 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
44 . = ALIGN(8);
45 __RT_SVC_DESCS_START__ = .;
46 KEEP(*(rt_svc_descs))
47 __RT_SVC_DESCS_END__ = .;
48
49#if ENABLE_PMF
50 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
51 . = ALIGN(8);
52 __PMF_SVC_DESCS_START__ = .;
53 KEEP(*(pmf_svc_descs))
54 __PMF_SVC_DESCS_END__ = .;
55#endif /* ENABLE_PMF */
56
57 /*
58 * Ensure 8-byte alignment for cpu_ops so that its fields are also
59 * aligned. Also ensure cpu_ops inclusion.
60 */
61 . = ALIGN(8);
62 __CPU_OPS_START__ = .;
63 KEEP(*(cpu_ops))
64 __CPU_OPS_END__ = .;
65
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010066 /* Place pubsub sections for events */
67 . = ALIGN(8);
68#include <pubsub_events.h>
69
Roberto Vargasd93fde32018-04-11 11:53:31 +010070 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010071 __RODATA_END__ = .;
72 } >RAM
73#else
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000074 ro . : {
75 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000076 *bl31_entrypoint.o(.text*)
77 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000078 *(.rodata*)
Achin Gupta7421b462014-02-01 18:53:26 +000079
Andrew Thoelkee01ea342014-03-18 07:13:52 +000080 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
Achin Gupta7421b462014-02-01 18:53:26 +000081 . = ALIGN(8);
82 __RT_SVC_DESCS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000083 KEEP(*(rt_svc_descs))
Achin Gupta7421b462014-02-01 18:53:26 +000084 __RT_SVC_DESCS_END__ = .;
85
Yatharth Kochar9518d022016-03-11 14:20:19 +000086#if ENABLE_PMF
87 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
88 . = ALIGN(8);
89 __PMF_SVC_DESCS_START__ = .;
90 KEEP(*(pmf_svc_descs))
91 __PMF_SVC_DESCS_END__ = .;
92#endif /* ENABLE_PMF */
93
Soby Mathewc704cbc2014-08-14 11:33:56 +010094 /*
95 * Ensure 8-byte alignment for cpu_ops so that its fields are also
96 * aligned. Also ensure cpu_ops inclusion.
97 */
98 . = ALIGN(8);
99 __CPU_OPS_START__ = .;
100 KEEP(*(cpu_ops))
101 __CPU_OPS_END__ = .;
102
Jeenu Viswambharane3f22002017-09-22 08:32:10 +0100103 /* Place pubsub sections for events */
104 . = ALIGN(8);
105#include <pubsub_events.h>
106
Achin Guptab739f222014-01-18 16:50:09 +0000107 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000108 __RO_END_UNALIGNED__ = .;
109 /*
110 * Memory page(s) mapped to this section will be marked as read-only,
111 * executable. No RW data from the next section must creep in.
112 * Ensure the rest of the current memory page is unused.
113 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100114 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000115 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +0100117#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100118
Soby Mathewc704cbc2014-08-14 11:33:56 +0100119 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
120 "cpu_ops not defined for this platform.")
121
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100122#if ENABLE_SPM
123 /*
124 * Exception vectors of the SPM shim layer. They must be aligned to a 2K
125 * address, but we need to place them in a separate page so that we can set
126 * individual permissions to them, so the actual alignment needed is 4K.
127 *
128 * There's no need to include this into the RO section of BL31 because it
129 * doesn't need to be accessed by BL31.
130 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000131 spm_shim_exceptions : ALIGN(PAGE_SIZE) {
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100132 __SPM_SHIM_EXCEPTIONS_START__ = .;
133 *(.spm_shim_exceptions)
Roberto Vargasd93fde32018-04-11 11:53:31 +0100134 . = ALIGN(PAGE_SIZE);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100135 __SPM_SHIM_EXCEPTIONS_END__ = .;
136 } >RAM
137#endif
138
Achin Guptae9c4a642015-09-11 16:03:13 +0100139 /*
140 * Define a linker symbol to mark start of the RW memory area for this
141 * image.
142 */
143 __RW_START__ = . ;
144
Douglas Raillard306593d2017-02-24 18:14:15 +0000145 /*
146 * .data must be placed at a lower address than the stacks if the stack
147 * protector is enabled. Alternatively, the .data.stack_protector_canary
148 * section can be placed independently of the main .data section.
149 */
150 .data . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000151 __DATA_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000152 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000153 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154 } >RAM
155
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +0100156#ifdef BL31_PROGBITS_LIMIT
Juan Castillo7d199412015-12-14 09:35:25 +0000157 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +0100158#endif
159
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000160 stacks (NOLOAD) : {
161 __STACKS_START__ = .;
162 *(tzfw_normal_stacks)
163 __STACKS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100164 } >RAM
165
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000166 /*
167 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +0000168 * Its base address should be 16-byte aligned for better performance of the
169 * zero-initialization code.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000170 */
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100171 .bss (NOLOAD) : ALIGN(16) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000172 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000173 *(.bss*)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100174 *(COMMON)
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100175#if !USE_COHERENT_MEM
176 /*
177 * Bakery locks are stored in normal .bss memory
178 *
179 * Each lock's data is spread across multiple cache lines, one per CPU,
180 * but multiple locks can share the same cache line.
181 * The compiler will allocate enough memory for one CPU's bakery locks,
182 * the remaining cache lines are allocated by the linker script
183 */
184 . = ALIGN(CACHE_WRITEBACK_GRANULE);
185 __BAKERY_LOCK_START__ = .;
186 *(bakery_lock)
187 . = ALIGN(CACHE_WRITEBACK_GRANULE);
Vikram Kanigiri405fafe2015-09-24 15:45:43 +0100188 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__);
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100189 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
190 __BAKERY_LOCK_END__ = .;
191#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
192 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE,
193 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
194#endif
195#endif
Yatharth Kochar9518d022016-03-11 14:20:19 +0000196
197#if ENABLE_PMF
198 /*
199 * Time-stamps are stored in normal .bss memory
200 *
201 * The compiler will allocate enough memory for one CPU's time-stamps,
202 * the remaining memory for other CPU's is allocated by the
203 * linker script
204 */
205 . = ALIGN(CACHE_WRITEBACK_GRANULE);
206 __PMF_TIMESTAMP_START__ = .;
207 KEEP(*(pmf_timestamp_array))
208 . = ALIGN(CACHE_WRITEBACK_GRANULE);
209 __PMF_PERCPU_TIMESTAMP_END__ = .;
210 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
211 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
212 __PMF_TIMESTAMP_END__ = .;
213#endif /* ENABLE_PMF */
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000214 __BSS_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100215 } >RAM
216
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000217 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +0000218 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +0000219 * Removing them from .bss avoids forcing 4K alignment on
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +0000220 * the .bss section. The tables are initialized to zero by the translation
221 * tables library.
Achin Guptaa0cd9892014-02-09 13:30:38 +0000222 */
223 xlat_table (NOLOAD) : {
224 *(xlat_table)
225 } >RAM
226
Soby Mathew2ae20432015-01-08 18:02:44 +0000227#if USE_COHERENT_MEM
Achin Guptaa0cd9892014-02-09 13:30:38 +0000228 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000229 * The base address of the coherent memory section must be page-aligned (4K)
230 * to guarantee that the coherent data are stored on their own pages and
231 * are not mixed with normal data. This is required to set up the correct
232 * memory attributes for the coherent data page tables.
233 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000234 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000235 __COHERENT_RAM_START__ = .;
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100236 /*
237 * Bakery locks are stored in coherent memory
238 *
239 * Each lock's data is contiguous and fully allocated by the compiler
240 */
241 *(bakery_lock)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000242 *(tzfw_coherent_mem)
243 __COHERENT_RAM_END_UNALIGNED__ = .;
244 /*
245 * Memory page(s) mapped to this section will be marked
246 * as device memory. No other unexpected data must creep in.
247 * Ensure the rest of the current memory page is unused.
248 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100249 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000250 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000252#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100253
Achin Guptae9c4a642015-09-11 16:03:13 +0100254 /*
255 * Define a linker symbol to mark end of the RW memory area for this
256 * image.
257 */
258 __RW_END__ = .;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000259 __BL31_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100260
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000261 __BSS_SIZE__ = SIZEOF(.bss);
Soby Mathew2ae20432015-01-08 18:02:44 +0000262#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000263 __COHERENT_RAM_UNALIGNED_SIZE__ =
264 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000265#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266
Juan Castillo7d199412015-12-14 09:35:25 +0000267 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100268}