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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#include <assert.h>
32#include <arch_helpers.h>
33#include <platform.h>
34#include <bl1.h>
35#include <console.h>
Harry Liebel30affd52013-10-30 17:41:48 +000036#include <cci400.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010037
38/*******************************************************************************
39 * Declarations of linker defined symbols which will help us find the layout
40 * of trusted SRAM
41 ******************************************************************************/
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000042extern unsigned long __COHERENT_RAM_START__;
43extern unsigned long __COHERENT_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000045extern unsigned long __BL1_RAM_START__;
46extern unsigned long __BL1_RAM_END__;
Achin Gupta4f6ad662013-10-25 09:08:21 +010047
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000048/*
49 * The next 2 constants identify the extents of the coherent memory region.
50 * These addresses are used by the MMU setup code and therefore they must be
51 * page-aligned. It is the responsibility of the linker script to ensure that
52 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
53 * page-aligned addresses.
54 */
55#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
56#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010057
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000058#define BL1_RAM_BASE (unsigned long)(&__BL1_RAM_START__)
59#define BL1_RAM_LIMIT (unsigned long)(&__BL1_RAM_END__)
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
62/* Data structure which holds the extents of the trusted SRAM for BL1*/
Sandrine Bailleux204aa032013-10-28 15:14:00 +000063static meminfo bl1_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010064
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +000065meminfo *bl1_plat_sec_mem_layout(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +010066{
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +000067 return &bl1_tzram_layout;
Achin Gupta4f6ad662013-10-25 09:08:21 +010068}
69
70/*******************************************************************************
71 * Perform any BL1 specific platform actions.
72 ******************************************************************************/
73void bl1_early_platform_setup(void)
74{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000075 const unsigned long bl1_ram_base = BL1_RAM_BASE;
76 const unsigned long bl1_ram_limit = BL1_RAM_LIMIT;
77 const unsigned long tzram_limit = TZRAM_BASE + TZRAM_SIZE;
Achin Gupta4f6ad662013-10-25 09:08:21 +010078
79 /*
80 * Calculate how much ram is BL1 using & how much remains free.
81 * This also includes a rudimentary mechanism to detect whether
82 * the BL1 data is loaded at the top or bottom of memory.
83 * TODO: add support for discontigous chunks of free ram if
84 * needed. Might need dynamic memory allocation support
85 * et al.
Achin Gupta4f6ad662013-10-25 09:08:21 +010086 */
87 bl1_tzram_layout.total_base = TZRAM_BASE;
88 bl1_tzram_layout.total_size = TZRAM_SIZE;
89
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000090 if (bl1_ram_limit == tzram_limit) {
91 /* BL1 has been loaded at the top of memory. */
Achin Gupta4f6ad662013-10-25 09:08:21 +010092 bl1_tzram_layout.free_base = TZRAM_BASE;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000093 bl1_tzram_layout.free_size = bl1_ram_base - TZRAM_BASE;
Achin Gupta4f6ad662013-10-25 09:08:21 +010094 } else {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000095 /* BL1 has been loaded at the bottom of memory. */
96 bl1_tzram_layout.free_base = bl1_ram_limit;
Achin Gupta4f6ad662013-10-25 09:08:21 +010097 bl1_tzram_layout.free_size =
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000098 tzram_limit - bl1_ram_limit;
Achin Gupta4f6ad662013-10-25 09:08:21 +010099 }
Harry Liebel30affd52013-10-30 17:41:48 +0000100
101 /* Initialize the platform config for future decision making */
102 platform_config_setup();
Sandrine Bailleux7c596b22014-02-21 14:16:16 +0000103
104 /* Initialize the console */
105 console_init(PL011_UART0_BASE);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106}
107
108/*******************************************************************************
109 * Function which will evaluate how much of the trusted ram has been gobbled
110 * up by BL1 and return the base and size of whats available for loading BL2.
111 * Its called after coherency and the MMU have been turned on.
112 ******************************************************************************/
113void bl1_platform_setup(void)
114{
Jeenu Viswambharan57418942014-01-07 10:21:18 +0000115 unsigned int counter_base_frequency;
116
James Morrissey9d72b4e2014-02-10 17:04:32 +0000117 /* Initialise the IO layer and register platform IO devices */
118 io_setup();
119
Jeenu Viswambharan57418942014-01-07 10:21:18 +0000120 /*
121 * Enable and initialize the System level generic timer. Choose base
122 * frequency for the timer
123 */
124 mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF, CNTCR_FCREQ(0) | CNTCR_EN);
125
126 /* Read the frequency from Frequency modes table */
127 counter_base_frequency = mmio_read_32(SYS_CNTCTL_BASE + CNTFID_OFF);
128
129 /* The first entry of the frequency modes table must not be 0 */
130 assert(counter_base_frequency != 0);
131
132 /* Program the counter frequency */
133 write_cntfrq_el0(counter_base_frequency);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100134}
135
James Morrissey9d72b4e2014-02-10 17:04:32 +0000136
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137/*******************************************************************************
138 * Perform the very early platform specific architecture setup here. At the
Harry Liebel30affd52013-10-30 17:41:48 +0000139 * moment this only does basic initialization. Later architectural setup
140 * (bl1_arch_setup()) does not do anything platform specific.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141 ******************************************************************************/
142void bl1_plat_arch_setup(void)
143{
Harry Liebel30affd52013-10-30 17:41:48 +0000144 unsigned long cci_setup;
145
146 /*
147 * Enable CCI-400 for this cluster. No need
148 * for locks as no other cpu is active at the
149 * moment
150 */
151 cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
152 if (cci_setup) {
153 cci_enable_coherency(read_mpidr());
154 }
155
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156 configure_mmu(&bl1_tzram_layout,
Ian Spray84687392014-01-02 16:57:12 +0000157 TZROM_BASE,
158 TZROM_BASE + TZROM_SIZE,
159 BL1_COHERENT_RAM_BASE,
160 BL1_COHERENT_RAM_LIMIT);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100161}