johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
Bipin Ravi | 2f73d97 | 2022-01-20 00:01:04 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2022, Arm Limited. All rights reserved. |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_x2.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
| 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 24 | /* -------------------------------------------------- |
johpow01 | 0afef36 | 2021-12-02 13:25:50 -0600 | [diff] [blame] | 25 | * Errata Workaround for Cortex X2 Errata #2002765. |
| 26 | * This applies to revisions r0p0, r1p0, and r2p0 and |
| 27 | * is open. |
| 28 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 29 | * Shall clobber: x0, x1, x17 |
| 30 | * -------------------------------------------------- |
| 31 | */ |
| 32 | func errata_cortex_x2_2002765_wa |
| 33 | /* Check workaround compatibility. */ |
| 34 | mov x17, x30 |
| 35 | bl check_errata_2002765 |
| 36 | cbz x0, 1f |
| 37 | |
| 38 | ldr x0, =0x6 |
| 39 | msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ |
| 40 | ldr x0, =0xF3A08002 |
| 41 | msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ |
| 42 | ldr x0, =0xFFF0F7FE |
| 43 | msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ |
| 44 | ldr x0, =0x40000001003ff |
| 45 | msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ |
| 46 | isb |
| 47 | |
| 48 | 1: |
| 49 | ret x17 |
| 50 | endfunc errata_cortex_x2_2002765_wa |
| 51 | |
| 52 | func check_errata_2002765 |
| 53 | /* Applies to r0p0 - r2p0 */ |
| 54 | mov x1, #0x20 |
| 55 | b cpu_rev_var_ls |
| 56 | endfunc check_errata_2002765 |
| 57 | |
| 58 | /* -------------------------------------------------- |
johpow01 | f6c37de | 2021-12-03 11:27:33 -0600 | [diff] [blame] | 59 | * Errata Workaround for Cortex X2 Errata #2058056. |
| 60 | * This applies to revisions r0p0, r1p0, and r2p0 and |
| 61 | * is open. |
| 62 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 63 | * Shall clobber: x0, x1, x17 |
| 64 | * -------------------------------------------------- |
| 65 | */ |
| 66 | func errata_cortex_x2_2058056_wa |
| 67 | /* Check workaround compatibility. */ |
| 68 | mov x17, x30 |
| 69 | bl check_errata_2058056 |
| 70 | cbz x0, 1f |
| 71 | |
| 72 | mrs x1, CORTEX_X2_CPUECTLR2_EL1 |
| 73 | mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV |
| 74 | bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH |
| 75 | msr CORTEX_X2_CPUECTLR2_EL1, x1 |
| 76 | |
| 77 | 1: |
| 78 | ret x17 |
| 79 | endfunc errata_cortex_x2_2058056_wa |
| 80 | |
| 81 | func check_errata_2058056 |
| 82 | /* Applies to r0p0 - r2p0 */ |
| 83 | mov x1, #0x20 |
| 84 | b cpu_rev_var_ls |
| 85 | endfunc check_errata_2058056 |
| 86 | |
| 87 | /* -------------------------------------------------- |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 88 | * Errata Workaround for Cortex X2 Errata #2083908. |
| 89 | * This applies to revision r2p0 and is open. |
| 90 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 91 | * Shall clobber: x0-x2, x17 |
| 92 | * -------------------------------------------------- |
| 93 | */ |
| 94 | func errata_cortex_x2_2083908_wa |
| 95 | /* Check workaround compatibility. */ |
| 96 | mov x17, x30 |
| 97 | bl check_errata_2083908 |
| 98 | cbz x0, 1f |
| 99 | |
| 100 | /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ |
| 101 | mrs x1, CORTEX_X2_CPUACTLR5_EL1 |
| 102 | orr x1, x1, #BIT(13) |
| 103 | msr CORTEX_X2_CPUACTLR5_EL1, x1 |
| 104 | |
| 105 | 1: |
| 106 | ret x17 |
| 107 | endfunc errata_cortex_x2_2083908_wa |
| 108 | |
| 109 | func check_errata_2083908 |
| 110 | /* Applies to r2p0 */ |
| 111 | mov x1, #0x20 |
| 112 | mov x2, #0x20 |
| 113 | b cpu_rev_var_range |
| 114 | endfunc check_errata_2083908 |
| 115 | |
Bipin Ravi | 2f73d97 | 2022-01-20 00:01:04 -0600 | [diff] [blame] | 116 | /* -------------------------------------------------- |
| 117 | * Errata Workaround for Cortex-X2 Errata 2017096. |
| 118 | * This applies only to revisions r0p0, r1p0 and r2p0 |
| 119 | * and is fixed in r2p1. |
| 120 | * Inputs: |
| 121 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 122 | * Shall clobber: x0, x1, x17 |
| 123 | * -------------------------------------------------- |
| 124 | */ |
| 125 | func errata_x2_2017096_wa |
| 126 | /* Compare x0 against revision r0p0 to r2p0 */ |
| 127 | mov x17, x30 |
| 128 | bl check_errata_2017096 |
| 129 | cbz x0, 1f |
| 130 | mrs x1, CORTEX_X2_CPUECTLR_EL1 |
| 131 | orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT |
| 132 | msr CORTEX_X2_CPUECTLR_EL1, x1 |
| 133 | |
| 134 | 1: |
| 135 | ret x17 |
| 136 | endfunc errata_x2_2017096_wa |
| 137 | |
| 138 | func check_errata_2017096 |
| 139 | /* Applies to r0p0, r1p0, r2p0 */ |
| 140 | mov x1, #0x20 |
| 141 | b cpu_rev_var_ls |
| 142 | endfunc check_errata_2017096 |
| 143 | |
Bipin Ravi | 9ad5478 | 2022-01-20 00:42:05 -0600 | [diff] [blame] | 144 | /* -------------------------------------------------- |
| 145 | * Errata Workaround for Cortex-X2 Errata 2081180. |
| 146 | * This applies to revision r0p0, r1p0 and r2p0 |
| 147 | * and is fixed in r2p1. |
| 148 | * Inputs: |
| 149 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 150 | * Shall clobber: x0, x1, x17 |
| 151 | * -------------------------------------------------- |
| 152 | */ |
| 153 | func errata_x2_2081180_wa |
| 154 | /* Check revision. */ |
| 155 | mov x17, x30 |
| 156 | bl check_errata_2081180 |
| 157 | cbz x0, 1f |
| 158 | |
| 159 | /* Apply instruction patching sequence */ |
| 160 | ldr x0, =0x3 |
| 161 | msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 |
| 162 | ldr x0, =0xF3A08002 |
| 163 | msr CORTEX_X2_IMP_CPUPOR_EL3, x0 |
| 164 | ldr x0, =0xFFF0F7FE |
| 165 | msr CORTEX_X2_IMP_CPUPMR_EL3, x0 |
| 166 | ldr x0, =0x10002001003FF |
| 167 | msr CORTEX_X2_IMP_CPUPCR_EL3, x0 |
| 168 | ldr x0, =0x4 |
| 169 | msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 |
| 170 | ldr x0, =0xBF200000 |
| 171 | msr CORTEX_X2_IMP_CPUPOR_EL3, x0 |
| 172 | ldr x0, =0xFFEF0000 |
| 173 | msr CORTEX_X2_IMP_CPUPMR_EL3, x0 |
| 174 | ldr x0, =0x10002001003F3 |
| 175 | msr CORTEX_X2_IMP_CPUPCR_EL3, x0 |
| 176 | isb |
| 177 | 1: |
| 178 | ret x17 |
| 179 | endfunc errata_x2_2081180_wa |
| 180 | |
| 181 | func check_errata_2081180 |
| 182 | /* Applies to r0p0, r1p0 and r2p0 */ |
| 183 | mov x1, #0x20 |
| 184 | b cpu_rev_var_ls |
| 185 | endfunc check_errata_2081180 |
| 186 | |
Bipin Ravi | 78b7208 | 2022-02-06 01:29:31 -0600 | [diff] [blame] | 187 | /* -------------------------------------------------- |
| 188 | * Errata Workaround for Cortex X2 Errata 2216384. |
| 189 | * This applies to revisions r0p0, r1p0, and r2p0 |
| 190 | * and is fixed in r2p1. |
| 191 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 192 | * Shall clobber: x0, x1, x17 |
| 193 | * -------------------------------------------------- |
| 194 | */ |
| 195 | func errata_x2_2216384_wa |
| 196 | /* Check workaround compatibility. */ |
| 197 | mov x17, x30 |
| 198 | bl check_errata_2216384 |
| 199 | cbz x0, 1f |
| 200 | |
| 201 | mrs x1, CORTEX_X2_CPUACTLR5_EL1 |
| 202 | orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17 |
| 203 | msr CORTEX_X2_CPUACTLR5_EL1, x1 |
| 204 | |
| 205 | /* Apply instruction patching sequence */ |
| 206 | ldr x0, =0x5 |
| 207 | msr CORTEX_X2_IMP_CPUPSELR_EL3, x0 |
| 208 | ldr x0, =0x10F600E000 |
| 209 | msr CORTEX_X2_IMP_CPUPOR_EL3, x0 |
| 210 | ldr x0, =0x10FF80E000 |
| 211 | msr CORTEX_X2_IMP_CPUPMR_EL3, x0 |
| 212 | ldr x0, =0x80000000003FF |
| 213 | msr CORTEX_X2_IMP_CPUPCR_EL3, x0 |
| 214 | isb |
| 215 | |
| 216 | 1: |
| 217 | ret x17 |
| 218 | endfunc errata_x2_2216384_wa |
| 219 | |
| 220 | func check_errata_2216384 |
| 221 | /* Applies to r0p0 - r2p0 */ |
| 222 | mov x1, #0x20 |
| 223 | b cpu_rev_var_ls |
| 224 | endfunc check_errata_2216384 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 225 | /* ---------------------------------------------------- |
| 226 | * HW will do the cache maintenance while powering down |
| 227 | * ---------------------------------------------------- |
| 228 | */ |
| 229 | func cortex_x2_core_pwr_dwn |
| 230 | /* --------------------------------------------------- |
| 231 | * Enable CPU power down bit in power control register |
| 232 | * --------------------------------------------------- |
| 233 | */ |
| 234 | mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 |
| 235 | orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 236 | msr CORTEX_X2_CPUPWRCTLR_EL1, x0 |
| 237 | isb |
| 238 | ret |
| 239 | endfunc cortex_x2_core_pwr_dwn |
| 240 | |
| 241 | /* |
| 242 | * Errata printing function for Cortex X2. Must follow AAPCS. |
| 243 | */ |
| 244 | #if REPORT_ERRATA |
| 245 | func cortex_x2_errata_report |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 246 | stp x8, x30, [sp, #-16]! |
| 247 | |
| 248 | bl cpu_get_rev_var |
| 249 | mov x8, x0 |
| 250 | |
| 251 | /* |
| 252 | * Report all errata. The revision-variant information is passed to |
| 253 | * checking functions of each errata. |
| 254 | */ |
johpow01 | 0afef36 | 2021-12-02 13:25:50 -0600 | [diff] [blame] | 255 | report_errata ERRATA_X2_2002765, cortex_x2, 2002765 |
johpow01 | f6c37de | 2021-12-03 11:27:33 -0600 | [diff] [blame] | 256 | report_errata ERRATA_X2_2058056, cortex_x2, 2058056 |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 257 | report_errata ERRATA_X2_2083908, cortex_x2, 2083908 |
Bipin Ravi | 2f73d97 | 2022-01-20 00:01:04 -0600 | [diff] [blame] | 258 | report_errata ERRATA_X2_2017096, cortex_x2, 2017096 |
Bipin Ravi | 9ad5478 | 2022-01-20 00:42:05 -0600 | [diff] [blame] | 259 | report_errata ERRATA_X2_2081180, cortex_x2, 2081180 |
Bipin Ravi | 78b7208 | 2022-02-06 01:29:31 -0600 | [diff] [blame] | 260 | report_errata ERRATA_X2_2216384, cortex_x2, 2216384 |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 261 | |
| 262 | ldp x8, x30, [sp], #16 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 263 | ret |
| 264 | endfunc cortex_x2_errata_report |
| 265 | #endif |
| 266 | |
| 267 | func cortex_x2_reset_func |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 268 | mov x19, x30 |
| 269 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 270 | /* Disable speculative loads */ |
| 271 | msr SSBS, xzr |
| 272 | isb |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 273 | |
| 274 | /* Get the CPU revision and stash it in x18. */ |
| 275 | bl cpu_get_rev_var |
| 276 | mov x18, x0 |
| 277 | |
johpow01 | 0afef36 | 2021-12-02 13:25:50 -0600 | [diff] [blame] | 278 | #if ERRATA_X2_2002765 |
| 279 | mov x0, x18 |
| 280 | bl errata_cortex_x2_2002765_wa |
| 281 | #endif |
| 282 | |
johpow01 | f6c37de | 2021-12-03 11:27:33 -0600 | [diff] [blame] | 283 | #if ERRATA_X2_2058056 |
| 284 | mov x0, x18 |
| 285 | bl errata_cortex_x2_2058056_wa |
| 286 | #endif |
| 287 | |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 288 | #if ERRATA_X2_2083908 |
| 289 | mov x0, x18 |
| 290 | bl errata_cortex_x2_2083908_wa |
| 291 | #endif |
| 292 | |
Bipin Ravi | 2f73d97 | 2022-01-20 00:01:04 -0600 | [diff] [blame] | 293 | #if ERRATA_X2_2017096 |
| 294 | mov x0, x18 |
| 295 | bl errata_x2_2017096_wa |
| 296 | #endif |
| 297 | |
Bipin Ravi | 9ad5478 | 2022-01-20 00:42:05 -0600 | [diff] [blame] | 298 | #if ERRATA_X2_2081180 |
| 299 | mov x0, x18 |
| 300 | bl errata_x2_2081180_wa |
| 301 | #endif |
| 302 | |
Bipin Ravi | 78b7208 | 2022-02-06 01:29:31 -0600 | [diff] [blame] | 303 | #if ERRATA_X2_2216384 |
| 304 | mov x0, x18 |
| 305 | bl errata_x2_2216384_wa |
| 306 | #endif |
| 307 | |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 308 | ret x19 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 309 | endfunc cortex_x2_reset_func |
| 310 | |
| 311 | /* --------------------------------------------- |
| 312 | * This function provides Cortex X2 specific |
| 313 | * register information for crash reporting. |
| 314 | * It needs to return with x6 pointing to |
| 315 | * a list of register names in ascii and |
| 316 | * x8 - x15 having values of registers to be |
| 317 | * reported. |
| 318 | * --------------------------------------------- |
| 319 | */ |
| 320 | .section .rodata.cortex_x2_regs, "aS" |
| 321 | cortex_x2_regs: /* The ascii list of register names to be reported */ |
| 322 | .asciz "cpuectlr_el1", "" |
| 323 | |
| 324 | func cortex_x2_cpu_reg_dump |
| 325 | adr x6, cortex_x2_regs |
| 326 | mrs x8, CORTEX_X2_CPUECTLR_EL1 |
| 327 | ret |
| 328 | endfunc cortex_x2_cpu_reg_dump |
| 329 | |
| 330 | declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ |
| 331 | cortex_x2_reset_func, \ |
| 332 | cortex_x2_core_pwr_dwn |