johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021, Arm Limited. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_x2.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
| 13 | |
| 14 | /* Hardware handled coherency */ |
| 15 | #if HW_ASSISTED_COHERENCY == 0 |
| 16 | #error "Cortex X2 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 17 | #endif |
| 18 | |
| 19 | /* 64-bit only core */ |
| 20 | #if CTX_INCLUDE_AARCH32_REGS == 1 |
| 21 | #error "Cortex X2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" |
| 22 | #endif |
| 23 | |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 24 | /* -------------------------------------------------- |
johpow01 | 0afef36 | 2021-12-02 13:25:50 -0600 | [diff] [blame^] | 25 | * Errata Workaround for Cortex X2 Errata #2002765. |
| 26 | * This applies to revisions r0p0, r1p0, and r2p0 and |
| 27 | * is open. |
| 28 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 29 | * Shall clobber: x0, x1, x17 |
| 30 | * -------------------------------------------------- |
| 31 | */ |
| 32 | func errata_cortex_x2_2002765_wa |
| 33 | /* Check workaround compatibility. */ |
| 34 | mov x17, x30 |
| 35 | bl check_errata_2002765 |
| 36 | cbz x0, 1f |
| 37 | |
| 38 | ldr x0, =0x6 |
| 39 | msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */ |
| 40 | ldr x0, =0xF3A08002 |
| 41 | msr S3_6_C15_C8_2, x0 /* CPUPOR_EL3 */ |
| 42 | ldr x0, =0xFFF0F7FE |
| 43 | msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */ |
| 44 | ldr x0, =0x40000001003ff |
| 45 | msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */ |
| 46 | isb |
| 47 | |
| 48 | 1: |
| 49 | ret x17 |
| 50 | endfunc errata_cortex_x2_2002765_wa |
| 51 | |
| 52 | func check_errata_2002765 |
| 53 | /* Applies to r0p0 - r2p0 */ |
| 54 | mov x1, #0x20 |
| 55 | b cpu_rev_var_ls |
| 56 | endfunc check_errata_2002765 |
| 57 | |
| 58 | /* -------------------------------------------------- |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 59 | * Errata Workaround for Cortex X2 Errata #2083908. |
| 60 | * This applies to revision r2p0 and is open. |
| 61 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 62 | * Shall clobber: x0-x2, x17 |
| 63 | * -------------------------------------------------- |
| 64 | */ |
| 65 | func errata_cortex_x2_2083908_wa |
| 66 | /* Check workaround compatibility. */ |
| 67 | mov x17, x30 |
| 68 | bl check_errata_2083908 |
| 69 | cbz x0, 1f |
| 70 | |
| 71 | /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */ |
| 72 | mrs x1, CORTEX_X2_CPUACTLR5_EL1 |
| 73 | orr x1, x1, #BIT(13) |
| 74 | msr CORTEX_X2_CPUACTLR5_EL1, x1 |
| 75 | |
| 76 | 1: |
| 77 | ret x17 |
| 78 | endfunc errata_cortex_x2_2083908_wa |
| 79 | |
| 80 | func check_errata_2083908 |
| 81 | /* Applies to r2p0 */ |
| 82 | mov x1, #0x20 |
| 83 | mov x2, #0x20 |
| 84 | b cpu_rev_var_range |
| 85 | endfunc check_errata_2083908 |
| 86 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 87 | /* ---------------------------------------------------- |
| 88 | * HW will do the cache maintenance while powering down |
| 89 | * ---------------------------------------------------- |
| 90 | */ |
| 91 | func cortex_x2_core_pwr_dwn |
| 92 | /* --------------------------------------------------- |
| 93 | * Enable CPU power down bit in power control register |
| 94 | * --------------------------------------------------- |
| 95 | */ |
| 96 | mrs x0, CORTEX_X2_CPUPWRCTLR_EL1 |
| 97 | orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT |
| 98 | msr CORTEX_X2_CPUPWRCTLR_EL1, x0 |
| 99 | isb |
| 100 | ret |
| 101 | endfunc cortex_x2_core_pwr_dwn |
| 102 | |
| 103 | /* |
| 104 | * Errata printing function for Cortex X2. Must follow AAPCS. |
| 105 | */ |
| 106 | #if REPORT_ERRATA |
| 107 | func cortex_x2_errata_report |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 108 | stp x8, x30, [sp, #-16]! |
| 109 | |
| 110 | bl cpu_get_rev_var |
| 111 | mov x8, x0 |
| 112 | |
| 113 | /* |
| 114 | * Report all errata. The revision-variant information is passed to |
| 115 | * checking functions of each errata. |
| 116 | */ |
johpow01 | 0afef36 | 2021-12-02 13:25:50 -0600 | [diff] [blame^] | 117 | report_errata ERRATA_X2_2002765, cortex_x2, 2002765 |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 118 | report_errata ERRATA_X2_2083908, cortex_x2, 2083908 |
| 119 | |
| 120 | ldp x8, x30, [sp], #16 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 121 | ret |
| 122 | endfunc cortex_x2_errata_report |
| 123 | #endif |
| 124 | |
| 125 | func cortex_x2_reset_func |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 126 | mov x19, x30 |
| 127 | |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 128 | /* Disable speculative loads */ |
| 129 | msr SSBS, xzr |
| 130 | isb |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 131 | |
| 132 | /* Get the CPU revision and stash it in x18. */ |
| 133 | bl cpu_get_rev_var |
| 134 | mov x18, x0 |
| 135 | |
johpow01 | 0afef36 | 2021-12-02 13:25:50 -0600 | [diff] [blame^] | 136 | #if ERRATA_X2_2002765 |
| 137 | mov x0, x18 |
| 138 | bl errata_cortex_x2_2002765_wa |
| 139 | #endif |
| 140 | |
johpow01 | 15f10bd | 2021-12-01 17:40:39 -0600 | [diff] [blame] | 141 | #if ERRATA_X2_2083908 |
| 142 | mov x0, x18 |
| 143 | bl errata_cortex_x2_2083908_wa |
| 144 | #endif |
| 145 | |
| 146 | ret x19 |
johpow01 | a3810e8 | 2021-05-18 15:23:31 -0500 | [diff] [blame] | 147 | endfunc cortex_x2_reset_func |
| 148 | |
| 149 | /* --------------------------------------------- |
| 150 | * This function provides Cortex X2 specific |
| 151 | * register information for crash reporting. |
| 152 | * It needs to return with x6 pointing to |
| 153 | * a list of register names in ascii and |
| 154 | * x8 - x15 having values of registers to be |
| 155 | * reported. |
| 156 | * --------------------------------------------- |
| 157 | */ |
| 158 | .section .rodata.cortex_x2_regs, "aS" |
| 159 | cortex_x2_regs: /* The ascii list of register names to be reported */ |
| 160 | .asciz "cpuectlr_el1", "" |
| 161 | |
| 162 | func cortex_x2_cpu_reg_dump |
| 163 | adr x6, cortex_x2_regs |
| 164 | mrs x8, CORTEX_X2_CPUECTLR_EL1 |
| 165 | ret |
| 166 | endfunc cortex_x2_cpu_reg_dump |
| 167 | |
| 168 | declare_cpu_ops cortex_x2, CORTEX_X2_MIDR, \ |
| 169 | cortex_x2_reset_func, \ |
| 170 | cortex_x2_core_pwr_dwn |