Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 7 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 14 | #include <context.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <drivers/console.h> |
| 16 | #include <lib/el3_runtime/context_mgmt.h> |
| 17 | #include <lib/mmio.h> |
| 18 | #include <lib/psci/psci.h> |
| 19 | #include <plat/common/platform.h> |
| 20 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 21 | #include <memctrl.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 22 | #include <pmc.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 23 | #include <tegra_def.h> |
| 24 | #include <tegra_private.h> |
| 25 | |
| 26 | extern uint64_t tegra_bl31_phys_base; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 27 | extern uint64_t tegra_sec_entry_point; |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 28 | extern uint64_t tegra_console_base; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 29 | |
| 30 | /* |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 31 | * tegra_fake_system_suspend acts as a boolean var controlling whether |
| 32 | * we are going to take fake system suspend code or normal system suspend code |
| 33 | * path. This variable is set inside the sip call handlers,when the kernel |
| 34 | * requests a SIP call to set the suspend debug flags. |
| 35 | */ |
| 36 | uint8_t tegra_fake_system_suspend; |
| 37 | |
| 38 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 39 | * The following platform setup functions are weakly defined. They |
| 40 | * provide typical implementations that will be overridden by a SoC. |
| 41 | */ |
Varun Wadekar | 99782e8 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 42 | #pragma weak tegra_soc_pwr_domain_suspend_pwrdown_early |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 43 | #pragma weak tegra_soc_pwr_domain_suspend |
| 44 | #pragma weak tegra_soc_pwr_domain_on |
| 45 | #pragma weak tegra_soc_pwr_domain_off |
| 46 | #pragma weak tegra_soc_pwr_domain_on_finish |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 47 | #pragma weak tegra_soc_pwr_domain_power_down_wfi |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 48 | #pragma weak tegra_soc_prepare_system_reset |
Varun Wadekar | e5caeed | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 49 | #pragma weak tegra_soc_prepare_system_off |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 50 | #pragma weak tegra_soc_get_target_pwr_state |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 51 | |
Varun Wadekar | 99782e8 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 52 | int tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) |
| 53 | { |
| 54 | return PSCI_E_NOT_SUPPORTED; |
| 55 | } |
| 56 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 57 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 58 | { |
| 59 | return PSCI_E_NOT_SUPPORTED; |
| 60 | } |
| 61 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 62 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 63 | { |
| 64 | return PSCI_E_SUCCESS; |
| 65 | } |
| 66 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 67 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 68 | { |
| 69 | return PSCI_E_SUCCESS; |
| 70 | } |
| 71 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 72 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 73 | { |
| 74 | return PSCI_E_SUCCESS; |
| 75 | } |
| 76 | |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 77 | int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
| 78 | { |
| 79 | return PSCI_E_SUCCESS; |
| 80 | } |
| 81 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 82 | int tegra_soc_prepare_system_reset(void) |
| 83 | { |
| 84 | return PSCI_E_SUCCESS; |
| 85 | } |
| 86 | |
Varun Wadekar | e5caeed | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 87 | __dead2 void tegra_soc_prepare_system_off(void) |
| 88 | { |
| 89 | ERROR("Tegra System Off: operation not handled.\n"); |
| 90 | panic(); |
| 91 | } |
| 92 | |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 93 | plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, |
| 94 | const plat_local_state_t *states, |
| 95 | unsigned int ncpu) |
| 96 | { |
Varun Wadekar | 14eaede | 2016-09-01 14:51:59 -0700 | [diff] [blame] | 97 | plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 98 | |
| 99 | assert(ncpu); |
| 100 | |
| 101 | do { |
| 102 | temp = *states++; |
Varun Wadekar | 14eaede | 2016-09-01 14:51:59 -0700 | [diff] [blame] | 103 | if ((temp < target)) |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 104 | target = temp; |
| 105 | } while (--ncpu); |
| 106 | |
| 107 | return target; |
| 108 | } |
| 109 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 110 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 111 | * This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND` |
| 112 | * call to get the `power_state` parameter. This allows the platform to encode |
| 113 | * the appropriate State-ID field within the `power_state` parameter which can |
| 114 | * be utilized in `pwr_domain_suspend()` to suspend to system affinity level. |
| 115 | ******************************************************************************/ |
| 116 | void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 117 | { |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 118 | /* all affinities use system suspend state id */ |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 119 | for (uint32_t i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 120 | req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | /******************************************************************************* |
| 124 | * Handler called when an affinity instance is about to enter standby. |
| 125 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 126 | void tegra_cpu_standby(plat_local_state_t cpu_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 127 | { |
| 128 | /* |
| 129 | * Enter standby state |
| 130 | * dsb is good practice before using wfi to enter low power states |
| 131 | */ |
| 132 | dsb(); |
| 133 | wfi(); |
| 134 | } |
| 135 | |
| 136 | /******************************************************************************* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 137 | * Handler called when an affinity instance is about to be turned on. The |
| 138 | * level and mpidr determine the affinity instance. |
| 139 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 140 | int tegra_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 141 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 142 | return tegra_soc_pwr_domain_on(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 146 | * Handler called when a power domain is about to be turned off. The |
| 147 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 148 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 149 | void tegra_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 150 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 151 | tegra_soc_pwr_domain_off(target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | /******************************************************************************* |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 155 | * Handler called when a power domain is about to be suspended. The |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 156 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | 99782e8 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 157 | * This handler is called with SMP and data cache enabled, when |
| 158 | * HW_ASSISTED_COHERENCY = 0 |
| 159 | ******************************************************************************/ |
| 160 | void tegra_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) |
| 161 | { |
| 162 | tegra_soc_pwr_domain_suspend_pwrdown_early(target_state); |
| 163 | } |
| 164 | |
| 165 | /******************************************************************************* |
| 166 | * Handler called when a power domain is about to be suspended. The |
| 167 | * target_state encodes the power state that each level should transition to. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 168 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 169 | void tegra_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 170 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 171 | tegra_soc_pwr_domain_suspend(target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 172 | |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 173 | /* Disable console if we are entering deep sleep. */ |
| 174 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 175 | PSTATE_ID_SOC_POWERDN) |
| 176 | console_uninit(); |
| 177 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 178 | /* disable GICC */ |
| 179 | tegra_gic_cpuif_deactivate(); |
| 180 | } |
| 181 | |
| 182 | /******************************************************************************* |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 183 | * Handler called at the end of the power domain suspend sequence. The |
| 184 | * target_state encodes the power state that each level should transition to. |
| 185 | ******************************************************************************/ |
| 186 | __dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t |
| 187 | *target_state) |
| 188 | { |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 189 | uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; |
| 190 | uint64_t rmr_el3 = 0; |
| 191 | |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 192 | /* call the chip's power down handler */ |
| 193 | tegra_soc_pwr_domain_power_down_wfi(target_state); |
| 194 | |
Vignesh Radhakrishnan | b4a7294 | 2017-03-03 10:58:05 -0800 | [diff] [blame] | 195 | /* |
| 196 | * If we are in fake system suspend mode, ensure we start doing |
| 197 | * procedures that help in looping back towards system suspend exit |
| 198 | * instead of calling WFI by requesting a warm reset. |
| 199 | * Else, just call WFI to enter low power state. |
| 200 | */ |
| 201 | if ((tegra_fake_system_suspend != 0U) && |
| 202 | (pwr_state == (uint8_t)PSTATE_ID_SOC_POWERDN)) { |
| 203 | |
| 204 | /* warm reboot */ |
| 205 | rmr_el3 = read_rmr_el3(); |
| 206 | write_rmr_el3(rmr_el3 | RMR_WARM_RESET_CPU); |
| 207 | |
| 208 | } else { |
| 209 | /* enter power down state */ |
| 210 | wfi(); |
| 211 | } |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 212 | |
| 213 | /* we can never reach here */ |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 214 | panic(); |
| 215 | } |
| 216 | |
| 217 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 218 | * Handler called when a power domain has just been powered on after |
| 219 | * being turned off earlier. The target_state encodes the low power state that |
| 220 | * each level has woken up from. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 221 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 222 | void tegra_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 223 | { |
| 224 | plat_params_from_bl2_t *plat_params; |
| 225 | |
| 226 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 227 | * Initialize the GIC cpu and distributor interfaces |
| 228 | */ |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 229 | plat_gic_setup(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 230 | |
| 231 | /* |
| 232 | * Check if we are exiting from deep sleep. |
| 233 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 234 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 235 | PSTATE_ID_SOC_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 236 | |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 237 | /* Initialize the runtime console */ |
Damon Duan | 777baa5 | 2016-11-07 19:37:50 +0800 | [diff] [blame] | 238 | if (tegra_console_base != (uint64_t)0) { |
| 239 | console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ, |
| 240 | TEGRA_CONSOLE_BAUDRATE); |
| 241 | } |
Varun Wadekar | a2c6be6 | 2016-08-01 22:16:21 -0700 | [diff] [blame] | 242 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 243 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 244 | * Restore Memory Controller settings as it loses state |
| 245 | * during system suspend. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 246 | */ |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 247 | tegra_memctrl_restore_settings(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 248 | |
| 249 | /* |
| 250 | * Security configuration to allow DRAM/device access. |
| 251 | */ |
| 252 | plat_params = bl31_get_plat_params(); |
Varun Wadekar | 6bb6246 | 2015-10-06 12:49:31 +0530 | [diff] [blame] | 253 | tegra_memctrl_tzdram_setup(plat_params->tzdram_base, |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 254 | plat_params->tzdram_size); |
Varun Wadekar | d5f578a | 2016-06-01 19:34:37 -0700 | [diff] [blame] | 255 | |
| 256 | /* |
| 257 | * Set up the TZRAM memory aperture to allow only secure world |
| 258 | * access |
| 259 | */ |
| 260 | tegra_memctrl_tzram_setup(TEGRA_TZRAM_BASE, TEGRA_TZRAM_SIZE); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 261 | } |
| 262 | |
| 263 | /* |
| 264 | * Reset hardware settings. |
| 265 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 266 | tegra_soc_pwr_domain_on_finish(target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 267 | } |
| 268 | |
| 269 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 270 | * Handler called when a power domain has just been powered on after |
| 271 | * having been suspended earlier. The target_state encodes the low power state |
| 272 | * that each level has woken up from. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 273 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 274 | void tegra_pwr_domain_suspend_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 275 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 276 | tegra_pwr_domain_on_finish(target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 277 | } |
| 278 | |
| 279 | /******************************************************************************* |
| 280 | * Handler called when the system wants to be powered off |
| 281 | ******************************************************************************/ |
| 282 | __dead2 void tegra_system_off(void) |
| 283 | { |
Varun Wadekar | e5caeed | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 284 | INFO("Powering down system...\n"); |
| 285 | |
| 286 | tegra_soc_prepare_system_off(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 287 | } |
| 288 | |
| 289 | /******************************************************************************* |
| 290 | * Handler called when the system wants to be restarted. |
| 291 | ******************************************************************************/ |
| 292 | __dead2 void tegra_system_reset(void) |
| 293 | { |
Varun Wadekar | e5caeed | 2016-01-07 14:04:21 -0800 | [diff] [blame] | 294 | INFO("Restarting system...\n"); |
| 295 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 296 | /* per-SoC system reset handler */ |
| 297 | tegra_soc_prepare_system_reset(); |
| 298 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 299 | /* |
| 300 | * Program the PMC in order to restart the system. |
| 301 | */ |
| 302 | tegra_pmc_system_reset(); |
| 303 | } |
| 304 | |
| 305 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 306 | * Handler called to check the validity of the power state parameter. |
| 307 | ******************************************************************************/ |
| 308 | int32_t tegra_validate_power_state(unsigned int power_state, |
| 309 | psci_power_state_t *req_state) |
| 310 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 311 | assert(req_state); |
| 312 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 313 | return tegra_soc_validate_power_state(power_state, req_state); |
| 314 | } |
| 315 | |
| 316 | /******************************************************************************* |
| 317 | * Platform handler called to check the validity of the non secure entrypoint. |
| 318 | ******************************************************************************/ |
| 319 | int tegra_validate_ns_entrypoint(uintptr_t entrypoint) |
| 320 | { |
| 321 | /* |
| 322 | * Check if the non secure entrypoint lies within the non |
| 323 | * secure DRAM. |
| 324 | */ |
| 325 | if ((entrypoint >= TEGRA_DRAM_BASE) && (entrypoint <= TEGRA_DRAM_END)) |
| 326 | return PSCI_E_SUCCESS; |
| 327 | |
| 328 | return PSCI_E_INVALID_ADDRESS; |
| 329 | } |
| 330 | |
| 331 | /******************************************************************************* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 332 | * Export the platform handlers to enable psci to invoke them |
| 333 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 334 | static const plat_psci_ops_t tegra_plat_psci_ops = { |
| 335 | .cpu_standby = tegra_cpu_standby, |
| 336 | .pwr_domain_on = tegra_pwr_domain_on, |
| 337 | .pwr_domain_off = tegra_pwr_domain_off, |
Varun Wadekar | 99782e8 | 2017-07-05 17:44:12 -0700 | [diff] [blame] | 338 | .pwr_domain_suspend_pwrdown_early = tegra_pwr_domain_suspend_pwrdown_early, |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 339 | .pwr_domain_suspend = tegra_pwr_domain_suspend, |
| 340 | .pwr_domain_on_finish = tegra_pwr_domain_on_finish, |
| 341 | .pwr_domain_suspend_finish = tegra_pwr_domain_suspend_finish, |
Varun Wadekar | d22429d | 2016-03-18 14:35:28 -0700 | [diff] [blame] | 342 | .pwr_domain_pwr_down_wfi = tegra_pwr_domain_power_down_wfi, |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 343 | .system_off = tegra_system_off, |
| 344 | .system_reset = tegra_system_reset, |
| 345 | .validate_power_state = tegra_validate_power_state, |
| 346 | .validate_ns_entrypoint = tegra_validate_ns_entrypoint, |
| 347 | .get_sys_suspend_power_state = tegra_get_sys_suspend_power_state, |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 348 | }; |
| 349 | |
| 350 | /******************************************************************************* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 351 | * Export the platform specific power ops and initialize Power Controller |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 352 | ******************************************************************************/ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 353 | int plat_setup_psci_ops(uintptr_t sec_entrypoint, |
| 354 | const plat_psci_ops_t **psci_ops) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 355 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 356 | psci_power_state_t target_state = { { PSCI_LOCAL_STATE_RUN } }; |
| 357 | |
| 358 | /* |
| 359 | * Flush entrypoint variable to PoC since it will be |
| 360 | * accessed after a reset with the caches turned off. |
| 361 | */ |
| 362 | tegra_sec_entry_point = sec_entrypoint; |
| 363 | flush_dcache_range((uint64_t)&tegra_sec_entry_point, sizeof(uint64_t)); |
| 364 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 365 | /* |
| 366 | * Reset hardware settings. |
| 367 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 368 | tegra_soc_pwr_domain_on_finish(&target_state); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 369 | |
| 370 | /* |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 371 | * Initialize PSCI ops struct |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 372 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 373 | *psci_ops = &tegra_plat_psci_ops; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 374 | |
| 375 | return 0; |
| 376 | } |
Varun Wadekar | 2497539 | 2016-05-05 14:13:30 -0700 | [diff] [blame] | 377 | |
| 378 | /******************************************************************************* |
| 379 | * Platform handler to calculate the proper target power level at the |
| 380 | * specified affinity level |
| 381 | ******************************************************************************/ |
| 382 | plat_local_state_t plat_get_target_pwr_state(unsigned int lvl, |
| 383 | const plat_local_state_t *states, |
| 384 | unsigned int ncpu) |
| 385 | { |
Varun Wadekar | f2aa1be | 2016-06-07 12:00:06 -0700 | [diff] [blame] | 386 | return tegra_soc_get_target_pwr_state(lvl, states, ncpu); |
Varun Wadekar | 2497539 | 2016-05-05 14:13:30 -0700 | [diff] [blame] | 387 | } |