blob: 0ad14a8001eeee551f93928b9181ef23aa4815fa [file] [log] [blame]
Konstantin Porotchkinede192d2018-10-08 16:48:52 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
Konstantin Porotchkinede192d2018-10-08 16:48:52 +03008#include <errno.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <common/debug.h>
11#include <drivers/delay_timer.h>
12#include <lib/mmio.h>
13#include <lib/spinlock.h>
14
Konstantin Porotchkinede192d2018-10-08 16:48:52 +030015#include <mvebu.h>
16#include <mvebu_def.h>
Pali Rohár52c1de52021-05-14 15:52:11 +020017#include <plat_marvell.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000018
Konstantin Porotchkinede192d2018-10-08 16:48:52 +030019#include "phy-comphy-3700.h"
20#include "phy-comphy-common.h"
21
22/*
23 * COMPHY_INDIRECT_REG points to ahci address space but the ahci region used in
24 * Linux is up to 0x178 so none will access it from Linux in runtime
25 * concurrently.
26 */
27#define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178)
28
29/* The USB3_GBE1_PHY range is above USB3 registers used in dts */
30#define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
31#define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
32
Konstantin Porotchkinede192d2018-10-08 16:48:52 +030033struct sgmii_phy_init_data_fix {
34 uint16_t addr;
35 uint16_t value;
36};
37
38/* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
39static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = {
40 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
41 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
42 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
43 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
44 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
45 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
46 {0x104, 0x0C10}
47};
48
49/* 40M1G25 mode init data */
50static uint16_t sgmii_phy_init[512] = {
51 /* 0 1 2 3 4 5 6 7 */
52 /*-----------------------------------------------------------*/
53 /* 8 9 A B C D E F */
54 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
55 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
56 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
57 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
58 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
59 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
60 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
61 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
62 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
63 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
64 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
65 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
66 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
67 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
68 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
69 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
70 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
71 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
72 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
73 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
74 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
75 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
76 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
77 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
78 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
79 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
80 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
81 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
82 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
83 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
84 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
85 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
86 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
87 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
88 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
89 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
90 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
92 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
93 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
94 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
95 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
96 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
97 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
98 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
99 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
100 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
101 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
103 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
116 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
118};
119
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300120/* PHY selector configures with corresponding modes */
Pali Rohár26a98622021-09-23 14:47:18 +0200121static int mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300122 uint32_t comphy_mode)
123{
124 uint32_t reg;
125 int mode = COMPHY_GET_MODE(comphy_mode);
126
127 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG);
128 switch (mode) {
129 case (COMPHY_SATA_MODE):
130 /* SATA must be in Lane2 */
131 if (comphy_index == COMPHY_LANE2)
132 reg &= ~COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
133 else
134 goto error;
135 break;
136
137 case (COMPHY_SGMII_MODE):
Pali Rohár51974d22021-08-27 11:16:43 +0200138 case (COMPHY_2500BASEX_MODE):
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300139 if (comphy_index == COMPHY_LANE0)
140 reg &= ~COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
141 else if (comphy_index == COMPHY_LANE1)
142 reg &= ~COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
143 else
144 goto error;
145 break;
146
147 case (COMPHY_USB3H_MODE):
148 case (COMPHY_USB3D_MODE):
149 case (COMPHY_USB3_MODE):
150 if (comphy_index == COMPHY_LANE2)
151 reg |= COMPHY_SELECTOR_USB3_PHY_SEL_BIT;
152 else if (comphy_index == COMPHY_LANE0)
153 reg |= COMPHY_SELECTOR_USB3_GBE1_SEL_BIT;
154 else
155 goto error;
156 break;
157
158 case (COMPHY_PCIE_MODE):
159 /* PCIE must be in Lane1 */
160 if (comphy_index == COMPHY_LANE1)
161 reg |= COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT;
162 else
163 goto error;
164 break;
165
166 default:
167 goto error;
168 }
169
170 mmio_write_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG, reg);
Pali Rohár26a98622021-09-23 14:47:18 +0200171 return 0;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300172error:
173 ERROR("COMPHY[%d] mode[%d] is invalid\n", comphy_index, mode);
Pali Rohár26a98622021-09-23 14:47:18 +0200174 return -EINVAL;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300175}
176
Marek Behún4f94cbc2019-11-05 15:21:54 +0100177/*
178 * This is something like the inverse of the previous function: for given
179 * lane it returns COMPHY_*_MODE.
180 *
181 * It is useful when powering the phy off.
182 *
183 * This function returns COMPHY_USB3_MODE even if the phy was configured
184 * with COMPHY_USB3D_MODE or COMPHY_USB3H_MODE. (The usb3 phy initialization
185 * code does not differentiate between these modes.)
186 * Also it returns COMPHY_SGMII_MODE even if the phy was configures with
Pali Rohár51974d22021-08-27 11:16:43 +0200187 * COMPHY_2500BASEX_MODE. (The sgmii phy initialization code does differentiate
Marek Behún4f94cbc2019-11-05 15:21:54 +0100188 * between these modes, but it is irrelevant when powering the phy off.)
189 */
190static int mvebu_a3700_comphy_get_mode(uint8_t comphy_index)
191{
192 uint32_t reg;
193
194 reg = mmio_read_32(MVEBU_COMPHY_REG_BASE + COMPHY_SELECTOR_PHY_REG);
195 switch (comphy_index) {
196 case COMPHY_LANE0:
197 if ((reg & COMPHY_SELECTOR_USB3_GBE1_SEL_BIT) != 0)
198 return COMPHY_USB3_MODE;
199 else
200 return COMPHY_SGMII_MODE;
201 case COMPHY_LANE1:
202 if ((reg & COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT) != 0)
203 return COMPHY_PCIE_MODE;
204 else
205 return COMPHY_SGMII_MODE;
206 case COMPHY_LANE2:
207 if ((reg & COMPHY_SELECTOR_USB3_PHY_SEL_BIT) != 0)
208 return COMPHY_USB3_MODE;
209 else
210 return COMPHY_SATA_MODE;
211 }
212
213 return COMPHY_UNUSED;
214}
215
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300216/* It is only used for SATA and USB3 on comphy lane2. */
217static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data,
Pali Rohár15b183c2021-09-23 14:11:25 +0200218 uint16_t mask, bool is_sata)
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300219{
220 /*
221 * When Lane 2 PHY is for USB3, access the PHY registers
222 * through indirect Address and Data registers:
223 * INDIR_ACC_PHY_ADDR (RD00E0178h [31:0]),
224 * INDIR_ACC_PHY_DATA (RD00E017Ch [31:0]),
225 * within the SATA Host Controller registers, Lane 2 base register
226 * offset is 0x200
227 */
Pali Rohár15b183c2021-09-23 14:11:25 +0200228 if (is_sata) {
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300229 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET, offset);
Pali Rohár15b183c2021-09-23 14:11:25 +0200230 } else {
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300231 mmio_write_32(addr + COMPHY_LANE2_INDIR_ADDR_OFFSET,
232 offset + USB3PHY_LANE2_REG_BASE_OFFSET);
Pali Rohár15b183c2021-09-23 14:11:25 +0200233 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300234
235 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask);
236}
237
Pali Rohár15b183c2021-09-23 14:11:25 +0200238/* It is only used for SATA on comphy lane2. */
239static void comphy_sata_set_indirect(uintptr_t addr, uint32_t reg_offset,
240 uint16_t data, uint16_t mask)
241{
242 comphy_set_indirect(addr, reg_offset, data, mask, true);
243}
244
245/* It is only used for USB3 indirect access on comphy lane2. */
246static void comphy_usb3_set_indirect(uintptr_t addr, uint32_t reg_offset,
247 uint16_t data, uint16_t mask)
248{
249 comphy_set_indirect(addr, reg_offset, data, mask, false);
250}
251
252/* It is only used for USB3 direct access not on comphy lane2. */
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300253static void comphy_usb3_set_direct(uintptr_t addr, uint32_t reg_offset,
Pali Rohár15b183c2021-09-23 14:11:25 +0200254 uint16_t data, uint16_t mask)
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300255{
256 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask);
257}
258
Pali Rohár58e99252021-09-23 15:08:00 +0200259static void comphy_sgmii_phy_init(uintptr_t sd_ip_addr, bool is_1gbps)
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300260{
261 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
262 int addr, fix_idx;
263 uint16_t val;
264
265 fix_idx = 0;
266 for (addr = 0; addr < 512; addr++) {
267 /*
268 * All PHY register values are defined in full for 3.125Gbps
269 * SERDES speed. The values required for 1.25 Gbps are almost
270 * the same and only few registers should be "fixed" in
271 * comparison to 3.125 Gbps values. These register values are
272 * stored in "sgmii_phy_init_fix" array.
273 */
Pali Rohár58e99252021-09-23 15:08:00 +0200274 if (!is_1gbps && sgmii_phy_init_fix[fix_idx].addr == addr) {
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300275 /* Use new value */
276 val = sgmii_phy_init_fix[fix_idx].value;
277 if (fix_idx < fix_arr_sz)
278 fix_idx++;
279 } else {
280 val = sgmii_phy_init[addr];
281 }
282
283 reg_set16(SGMIIPHY_ADDR(addr, sd_ip_addr), val, 0xFFFF);
284 }
285}
286
287static int mvebu_a3700_comphy_sata_power_on(uint8_t comphy_index,
288 uint32_t comphy_mode)
289{
Pali Rohár26a98622021-09-23 14:47:18 +0200290 int ret;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300291 uint32_t offset, data = 0, ref_clk;
292 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300293 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
294
295 debug_enter();
296
297 /* Configure phy selector for SATA */
Pali Rohár26a98622021-09-23 14:47:18 +0200298 ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
299 if (ret) {
300 return ret;
301 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300302
303 /* Clear phy isolation mode to make it work in normal mode */
304 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
Pali Rohár15b183c2021-09-23 14:11:25 +0200305 comphy_sata_set_indirect(comphy_indir_regs, offset, 0, PHY_ISOLATE_MODE);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300306
307 /* 0. Check the Polarity invert bits */
308 if (invert & COMPHY_POLARITY_TXD_INVERT)
309 data |= TXD_INVERT_BIT;
310 if (invert & COMPHY_POLARITY_RXD_INVERT)
311 data |= RXD_INVERT_BIT;
312
313 offset = COMPHY_SYNC_PATTERN_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
Pali Rohár15b183c2021-09-23 14:11:25 +0200314 comphy_sata_set_indirect(comphy_indir_regs, offset, data, TXD_INVERT_BIT |
315 RXD_INVERT_BIT);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300316
317 /* 1. Select 40-bit data width width */
318 offset = COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET;
Pali Rohár15b183c2021-09-23 14:11:25 +0200319 comphy_sata_set_indirect(comphy_indir_regs, offset, DATA_WIDTH_40BIT,
320 SEL_DATA_WIDTH_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300321
322 /* 2. Select reference clock(25M) and PHY mode (SATA) */
323 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
324 if (get_ref_clk() == 40)
325 ref_clk = REF_CLOCK_SPEED_40M;
326 else
327 ref_clk = REF_CLOCK_SPEED_25M;
328
Pali Rohár15b183c2021-09-23 14:11:25 +0200329 comphy_sata_set_indirect(comphy_indir_regs, offset, ref_clk | PHY_MODE_SATA,
330 REF_FREF_SEL_MASK | PHY_MODE_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300331
332 /* 3. Use maximum PLL rate (no power save) */
333 offset = COMPHY_KVCO_CAL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
Pali Rohár15b183c2021-09-23 14:11:25 +0200334 comphy_sata_set_indirect(comphy_indir_regs, offset, USE_MAX_PLL_RATE_BIT,
335 USE_MAX_PLL_RATE_BIT);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300336
337 /* 4. Reset reserved bit */
Pali Rohár15b183c2021-09-23 14:11:25 +0200338 comphy_sata_set_indirect(comphy_indir_regs, COMPHY_RESERVED_REG, 0,
339 PHYCTRL_FRM_PIN_BIT);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300340
341 /* 5. Set vendor-specific configuration (It is done in sata driver) */
342 /* XXX: in U-Boot below sequence was executed in this place, in Linux
343 * not. Now it is done only in U-Boot before this comphy
344 * initialization - tests shows that it works ok, but in case of any
345 * future problem it is left for reference.
346 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff);
347 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));
348 */
349
350 /* Wait for > 55 us to allow PLL be enabled */
351 udelay(PLL_SET_DELAY_US);
352
353 /* Polling status */
354 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
355 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
356
357 ret = polling_with_timeout(comphy_indir_regs +
358 COMPHY_LANE2_INDIR_DATA_OFFSET,
359 PLL_READY_TX_BIT, PLL_READY_TX_BIT,
360 COMPHY_PLL_TIMEOUT, REG_32BIT);
Pali Rohár26a98622021-09-23 14:47:18 +0200361 if (ret) {
362 return -ETIMEDOUT;
363 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300364
365 debug_exit();
366
Pali Rohár26a98622021-09-23 14:47:18 +0200367 return 0;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300368}
369
370static int mvebu_a3700_comphy_sgmii_power_on(uint8_t comphy_index,
371 uint32_t comphy_mode)
372{
Pali Rohár26a98622021-09-23 14:47:18 +0200373 int ret;
Pali Rohárc335e372021-09-23 18:19:24 +0200374 uint32_t mask, data;
375 uintptr_t offset;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300376 uintptr_t sd_ip_addr;
377 int mode = COMPHY_GET_MODE(comphy_mode);
378 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
379
380 debug_enter();
381
382 /* Set selector */
Pali Rohár26a98622021-09-23 14:47:18 +0200383 ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
384 if (ret) {
385 return ret;
386 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300387
388 /* Serdes IP Base address
389 * COMPHY Lane0 -- USB3/GBE1
390 * COMPHY Lane1 -- PCIe/GBE0
391 */
392 if (comphy_index == COMPHY_LANE0) {
393 /* Get usb3 and gbe */
394 sd_ip_addr = USB3_GBE1_PHY;
395 } else
396 sd_ip_addr = COMPHY_SD_ADDR;
397
398 /*
399 * 1. Reset PHY by setting PHY input port PIN_RESET=1.
400 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
401 * PHY TXP/TXN output to idle state during PHY initialization
402 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
403 */
404 data = PIN_PU_IVEREF_BIT | PIN_TX_IDLE_BIT | PIN_RESET_COMPHY_BIT;
405 mask = PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT |
406 PIN_PU_TX_BIT;
407 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
408 reg_set(offset, data, mask);
409
410 /* 4. Release reset to the PHY by setting PIN_RESET=0. */
411 data = 0;
412 mask = PIN_RESET_COMPHY_BIT;
413 reg_set(offset, data, mask);
414
415 /*
416 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY
417 * bit rate
418 */
419 if (mode == COMPHY_SGMII_MODE) {
420 /* SGMII 1G, SerDes speed 1.25G */
421 data |= SD_SPEED_1_25_G << GEN_RX_SEL_OFFSET;
422 data |= SD_SPEED_1_25_G << GEN_TX_SEL_OFFSET;
Pali Rohár51974d22021-08-27 11:16:43 +0200423 } else if (mode == COMPHY_2500BASEX_MODE) {
424 /* 2500Base-X, SerDes speed 3.125G */
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300425 data |= SD_SPEED_2_5_G << GEN_RX_SEL_OFFSET;
426 data |= SD_SPEED_2_5_G << GEN_TX_SEL_OFFSET;
427 } else {
428 /* Other rates are not supported */
429 ERROR("unsupported SGMII speed on comphy lane%d\n",
430 comphy_index);
431 return -EINVAL;
432 }
433 mask = GEN_RX_SEL_MASK | GEN_TX_SEL_MASK;
434 reg_set(offset, data, mask);
435
436 /*
437 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then
438 * start SW programming.
439 */
440 mdelay(10);
441
442 /* 7. Program COMPHY register PHY_MODE */
443 data = PHY_MODE_SGMII;
444 mask = PHY_MODE_MASK;
445 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask);
446
447 /*
448 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK
449 * source
450 */
451 data = 0;
452 mask = PHY_REF_CLK_SEL;
453 reg_set16(SGMIIPHY_ADDR(COMPHY_MISC_REG0_ADDR, sd_ip_addr), data, mask);
454
455 /*
456 * 9. Set correct reference clock frequency in COMPHY register
457 * REF_FREF_SEL.
458 */
459 if (get_ref_clk() == 40)
460 data = REF_CLOCK_SPEED_50M;
461 else
462 data = REF_CLOCK_SPEED_25M;
463
464 mask = REF_FREF_SEL_MASK;
465 reg_set16(SGMIIPHY_ADDR(COMPHY_POWER_PLL_CTRL, sd_ip_addr), data, mask);
466
467 /* 10. Program COMPHY register PHY_GEN_MAX[1:0]
468 * This step is mentioned in the flow received from verification team.
469 * However the PHY_GEN_MAX value is only meaningful for other interfaces
470 * (not SGMII). For instance, it selects SATA speed 1.5/3/6 Gbps or PCIe
471 * speed 2.5/5 Gbps
472 */
473
474 /*
475 * 11. Program COMPHY register SEL_BITS to set correct parallel data
476 * bus width
477 */
478 data = DATA_WIDTH_10BIT;
479 mask = SEL_DATA_WIDTH_MASK;
480 reg_set16(SGMIIPHY_ADDR(COMPHY_LOOPBACK_REG0, sd_ip_addr), data, mask);
481
482 /*
483 * 12. As long as DFE function needs to be enabled in any mode,
484 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
485 * for real chip during COMPHY power on.
486 * The step 14 exists (and empty) in the original initialization flow
487 * obtained from the verification team. According to the functional
488 * specification DFE_UPDATE_EN already has the default value 0x3F
489 */
490
491 /*
492 * 13. Program COMPHY GEN registers.
493 * These registers should be programmed based on the lab testing result
494 * to achieve optimal performance. Please contact the CEA group to get
495 * the related GEN table during real chip bring-up. We only required to
496 * run though the entire registers programming flow defined by
497 * "comphy_sgmii_phy_init" when the REF clock is 40 MHz. For REF clock
498 * 25 MHz the default values stored in PHY registers are OK.
499 */
500 debug("Running C-DPI phy init %s mode\n",
Pali Rohár51974d22021-08-27 11:16:43 +0200501 mode == COMPHY_2500BASEX_MODE ? "2G5" : "1G");
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300502 if (get_ref_clk() == 40)
Pali Rohár58e99252021-09-23 15:08:00 +0200503 comphy_sgmii_phy_init(sd_ip_addr, mode != COMPHY_2500BASEX_MODE);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300504
505 /*
506 * 14. [Simulation Only] should not be used for real chip.
507 * By pass power up calibration by programming EXT_FORCE_CAL_DONE
508 * (R02h[9]) to 1 to shorten COMPHY simulation time.
509 */
510
511 /*
512 * 15. [Simulation Only: should not be used for real chip]
513 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX training
514 * simulation time.
515 */
516
517 /*
518 * 16. Check the PHY Polarity invert bit
519 */
520 data = 0x0;
521 if (invert & COMPHY_POLARITY_TXD_INVERT)
522 data |= TXD_INVERT_BIT;
523 if (invert & COMPHY_POLARITY_RXD_INVERT)
524 data |= RXD_INVERT_BIT;
Pali Rohár741f7d62021-03-24 16:34:45 +0100525 mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
526 reg_set16(SGMIIPHY_ADDR(COMPHY_SYNC_PATTERN_REG, sd_ip_addr), data, mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300527
528 /*
529 * 17. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
530 * start PHY power up sequence. All the PHY register programming should
531 * be done before PIN_PU_PLL=1. There should be no register programming
532 * for normal PHY operation from this point.
533 */
534 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
535 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT,
536 PIN_PU_PLL_BIT | PIN_PU_RX_BIT | PIN_PU_TX_BIT);
537
538 /*
539 * 18. Wait for PHY power up sequence to finish by checking output ports
540 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
541 */
542 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
543 COMPHY_PHY_STATUS_OFFSET(comphy_index),
544 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
545 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
546 COMPHY_PLL_TIMEOUT, REG_32BIT);
Pali Rohár26a98622021-09-23 14:47:18 +0200547 if (ret) {
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300548 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index);
Pali Rohár26a98622021-09-23 14:47:18 +0200549 return -ETIMEDOUT;
550 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300551
552 /*
553 * 19. Set COMPHY input port PIN_TX_IDLE=0
554 */
555 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
556 0x0, PIN_TX_IDLE_BIT);
557
558 /*
559 * 20. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
560 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the
561 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to
562 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please
563 * refer to RX initialization part for details.
564 */
565 reg_set(MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index),
Pali Rohárc9ae2362021-03-24 16:40:46 +0100566 PHY_RX_INIT_BIT, PHY_RX_INIT_BIT);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300567
568 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
569 COMPHY_PHY_STATUS_OFFSET(comphy_index),
570 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
571 PHY_PLL_READY_TX_BIT | PHY_PLL_READY_RX_BIT,
572 COMPHY_PLL_TIMEOUT, REG_32BIT);
Pali Rohár26a98622021-09-23 14:47:18 +0200573 if (ret) {
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300574 ERROR("Failed to lock PLL for SGMII PHY %d\n", comphy_index);
Pali Rohár26a98622021-09-23 14:47:18 +0200575 return -ETIMEDOUT;
576 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300577
578 ret = polling_with_timeout(MVEBU_COMPHY_REG_BASE +
579 COMPHY_PHY_STATUS_OFFSET(comphy_index),
580 PHY_RX_INIT_DONE_BIT, PHY_RX_INIT_DONE_BIT,
581 COMPHY_PLL_TIMEOUT, REG_32BIT);
Pali Rohár26a98622021-09-23 14:47:18 +0200582 if (ret) {
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300583 ERROR("Failed to init RX of SGMII PHY %d\n", comphy_index);
Pali Rohár26a98622021-09-23 14:47:18 +0200584 return -ETIMEDOUT;
585 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300586
587 debug_exit();
588
Pali Rohár26a98622021-09-23 14:47:18 +0200589 return 0;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300590}
591
Marek Behún4f94cbc2019-11-05 15:21:54 +0100592static int mvebu_a3700_comphy_sgmii_power_off(uint8_t comphy_index)
593{
Pali Rohárc335e372021-09-23 18:19:24 +0200594 uintptr_t offset;
595 uint32_t mask, data;
Marek Behún4f94cbc2019-11-05 15:21:54 +0100596
597 debug_enter();
598
599 data = PIN_RESET_CORE_BIT | PIN_RESET_COMPHY_BIT;
Pali Rohárc9ae2362021-03-24 16:40:46 +0100600 mask = data;
Marek Behún4f94cbc2019-11-05 15:21:54 +0100601 offset = MVEBU_COMPHY_REG_BASE + COMPHY_PHY_CFG1_OFFSET(comphy_index);
602 reg_set(offset, data, mask);
603
604 debug_exit();
605
Pali Rohár26a98622021-09-23 14:47:18 +0200606 return 0;
Marek Behún4f94cbc2019-11-05 15:21:54 +0100607}
608
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300609static int mvebu_a3700_comphy_usb3_power_on(uint8_t comphy_index,
610 uint32_t comphy_mode)
611{
Pali Rohár26a98622021-09-23 14:47:18 +0200612 int ret;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300613 uintptr_t reg_base = 0;
Pali Rohárc335e372021-09-23 18:19:24 +0200614 uintptr_t addr;
615 uint32_t mask, data, cfg, ref_clk;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300616 void (*usb3_reg_set)(uintptr_t addr, uint32_t reg_offset, uint16_t data,
Pali Rohár15b183c2021-09-23 14:11:25 +0200617 uint16_t mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300618 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
619
620 debug_enter();
621
622 /* Set phy seclector */
Pali Rohár26a98622021-09-23 14:47:18 +0200623 ret = mvebu_a3700_comphy_set_phy_selector(comphy_index, comphy_mode);
624 if (ret) {
625 return ret;
626 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300627
628 /* Set usb3 reg access func, Lane2 is indirect access */
629 if (comphy_index == COMPHY_LANE2) {
Pali Rohár15b183c2021-09-23 14:11:25 +0200630 usb3_reg_set = &comphy_usb3_set_indirect;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300631 reg_base = COMPHY_INDIRECT_REG;
632 } else {
633 /* Get the direct access register resource and map */
634 usb3_reg_set = &comphy_usb3_set_direct;
635 reg_base = USB3_GBE1_PHY;
636 }
637
638 /*
639 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
640 * register belong to UTMI module, so it is set in UTMI phy driver.
641 */
642
643 /*
644 * 1. Set PRD_TXDEEMPH (3.5db de-emph)
645 */
646 mask = PRD_TXDEEMPH0_MASK | PRD_TXMARGIN_MASK | PRD_TXSWING_MASK |
647 CFG_TX_ALIGN_POS_MASK;
648 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG0_ADDR, PRD_TXDEEMPH0_MASK,
Pali Rohár15b183c2021-09-23 14:11:25 +0200649 mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300650
651 /*
652 * 2. Set BIT0: enable transmitter in high impedance mode
653 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
654 * Set BIT6: Tx detect Rx at HiZ mode
655 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
656 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR register
657 */
658 mask = PRD_TXDEEMPH1_MASK | TX_DET_RX_MODE | GEN2_TX_DATA_DLY_MASK |
659 TX_ELEC_IDLE_MODE_EN;
660 data = TX_DET_RX_MODE | GEN2_TX_DATA_DLY_DEFT | TX_ELEC_IDLE_MODE_EN;
Pali Rohár15b183c2021-09-23 14:11:25 +0200661 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG1_ADDR, data, mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300662
663 /*
664 * 3. Set Spread Spectrum Clock Enabled
665 */
666 usb3_reg_set(reg_base, COMPHY_REG_LANE_CFG4_ADDR,
Pali Rohár15b183c2021-09-23 14:11:25 +0200667 SPREAD_SPECTRUM_CLK_EN, SPREAD_SPECTRUM_CLK_EN);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300668
669 /*
670 * 4. Set Override Margining Controls From the MAC:
671 * Use margining signals from lane configuration
672 */
673 usb3_reg_set(reg_base, COMPHY_REG_TEST_MODE_CTRL_ADDR,
Pali Rohár15b183c2021-09-23 14:11:25 +0200674 MODE_MARGIN_OVERRIDE, REG_16_BIT_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300675
676 /*
677 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
678 * set Mode Clock Source = PCLK is generated from REFCLK
679 */
680 usb3_reg_set(reg_base, COMPHY_REG_GLOB_CLK_SRC_LO_ADDR, 0x0,
681 (MODE_CLK_SRC | BUNDLE_PERIOD_SEL | BUNDLE_PERIOD_SCALE |
Pali Rohár15b183c2021-09-23 14:11:25 +0200682 BUNDLE_SAMPLE_CTRL | PLL_READY_DLY));
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300683
684 /*
685 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K
686 */
687 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_2,
Pali Rohár15b183c2021-09-23 14:11:25 +0200688 G2_TX_SSC_AMP_VALUE_20, G2_TX_SSC_AMP_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300689
690 /*
691 * 7. Unset G3 Spread Spectrum Clock Amplitude
692 * set G3 TX and RX Register Master Current Select
693 */
694 mask = G3_TX_SSC_AMP_MASK | G3_VREG_RXTX_MAS_ISET_MASK |
695 RSVD_PH03FH_6_0_MASK;
696 usb3_reg_set(reg_base, COMPHY_REG_GEN2_SET_3,
Pali Rohár15b183c2021-09-23 14:11:25 +0200697 G3_VREG_RXTX_MAS_ISET_60U, mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300698
699 /*
700 * 8. Check crystal jumper setting and program the Power and PLL Control
701 * accordingly Change RX wait
702 */
703 if (get_ref_clk() == 40) {
704 ref_clk = REF_CLOCK_SPEED_40M;
705 cfg = CFG_PM_RXDLOZ_WAIT_12_UNIT;
706
707 } else {
708 /* 25 MHz */
709 ref_clk = USB3_REF_CLOCK_SPEED_25M;
710 cfg = CFG_PM_RXDLOZ_WAIT_7_UNIT;
711 }
712
713 mask = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
714 PU_TX_INTP_BIT | PU_DFE_BIT | PLL_LOCK_BIT | PHY_MODE_MASK |
715 REF_FREF_SEL_MASK;
716 data = PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
717 PU_TX_INTP_BIT | PU_DFE_BIT | PHY_MODE_USB3 | ref_clk;
Pali Rohár15b183c2021-09-23 14:11:25 +0200718 usb3_reg_set(reg_base, COMPHY_POWER_PLL_CTRL, data, mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300719
720 mask = CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
721 CFG_PM_RXDLOZ_WAIT_MASK;
722 data = CFG_PM_RXDEN_WAIT_1_UNIT | cfg;
Pali Rohár15b183c2021-09-23 14:11:25 +0200723 usb3_reg_set(reg_base, COMPHY_REG_PWR_MGM_TIM1_ADDR, data, mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300724
725 /*
726 * 9. Enable idle sync
727 */
728 data = UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN;
Pali Rohár15b183c2021-09-23 14:11:25 +0200729 usb3_reg_set(reg_base, COMPHY_REG_UNIT_CTRL_ADDR, data, REG_16_BIT_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300730
731 /*
732 * 10. Enable the output of 500M clock
733 */
734 data = MISC_REG0_DEFAULT_VALUE | CLK500M_EN;
Pali Rohár15b183c2021-09-23 14:11:25 +0200735 usb3_reg_set(reg_base, COMPHY_MISC_REG0_ADDR, data, REG_16_BIT_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300736
737 /*
738 * 11. Set 20-bit data width
739 */
740 usb3_reg_set(reg_base, COMPHY_LOOPBACK_REG0, DATA_WIDTH_20BIT,
Pali Rohár15b183c2021-09-23 14:11:25 +0200741 REG_16_BIT_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300742
743 /*
744 * 12. Override Speed_PLL value and use MAC PLL
745 */
746 usb3_reg_set(reg_base, COMPHY_KVCO_CAL_CTRL,
747 (SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT),
Pali Rohár15b183c2021-09-23 14:11:25 +0200748 REG_16_BIT_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300749
750 /*
751 * 13. Check the Polarity invert bit
752 */
Pali Rohár741f7d62021-03-24 16:34:45 +0100753 data = 0U;
754 if (invert & COMPHY_POLARITY_TXD_INVERT) {
755 data |= TXD_INVERT_BIT;
756 }
757 if (invert & COMPHY_POLARITY_RXD_INVERT) {
758 data |= RXD_INVERT_BIT;
759 }
760 mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
Pali Rohár15b183c2021-09-23 14:11:25 +0200761 usb3_reg_set(reg_base, COMPHY_SYNC_PATTERN_REG, data, mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300762
763 /*
764 * 14. Set max speed generation to USB3.0 5Gbps
765 */
766 usb3_reg_set(reg_base, COMPHY_SYNC_MASK_GEN_REG, PHY_GEN_USB3_5G,
Pali Rohár15b183c2021-09-23 14:11:25 +0200767 PHY_GEN_MAX_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300768
769 /*
770 * 15. Set capacitor value for FFE gain peaking to 0xF
771 */
772 usb3_reg_set(reg_base, COMPHY_REG_GEN3_SETTINGS_3,
Pali Rohár15b183c2021-09-23 14:11:25 +0200773 COMPHY_GEN_FFE_CAP_SEL_VALUE, COMPHY_GEN_FFE_CAP_SEL_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300774
775 /*
776 * 16. Release SW reset
777 */
778 data = MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32 | MODE_REFDIV_BY_4;
779 usb3_reg_set(reg_base, COMPHY_REG_GLOB_PHY_CTRL0_ADDR, data,
Pali Rohár15b183c2021-09-23 14:11:25 +0200780 REG_16_BIT_MASK);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300781
782 /* Wait for > 55 us to allow PCLK be enabled */
783 udelay(PLL_SET_DELAY_US);
784
785 if (comphy_index == COMPHY_LANE2) {
Marek Behún718e02c2019-10-08 17:36:14 +0200786 data = COMPHY_REG_LANE_STATUS1_ADDR + USB3PHY_LANE2_REG_BASE_OFFSET;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300787 mmio_write_32(reg_base + COMPHY_LANE2_INDIR_ADDR_OFFSET,
788 data);
789
Marek Behún718e02c2019-10-08 17:36:14 +0200790 addr = reg_base + COMPHY_LANE2_INDIR_DATA_OFFSET;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300791 ret = polling_with_timeout(addr, TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
792 COMPHY_PLL_TIMEOUT, REG_32BIT);
793 } else {
794 ret = polling_with_timeout(LANE_STATUS1_ADDR(USB3) + reg_base,
795 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
796 COMPHY_PLL_TIMEOUT, REG_16BIT);
797 }
Pali Rohár26a98622021-09-23 14:47:18 +0200798 if (ret) {
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300799 ERROR("Failed to lock USB3 PLL\n");
Pali Rohár26a98622021-09-23 14:47:18 +0200800 return -ETIMEDOUT;
801 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300802
803 debug_exit();
804
Pali Rohár26a98622021-09-23 14:47:18 +0200805 return 0;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300806}
807
808static int mvebu_a3700_comphy_pcie_power_on(uint8_t comphy_index,
809 uint32_t comphy_mode)
810{
811 int ret;
812 uint32_t ref_clk;
Pali Rohár741f7d62021-03-24 16:34:45 +0100813 uint32_t mask, data;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300814 int invert = COMPHY_GET_POLARITY_INVERT(comphy_mode);
815
816 debug_enter();
817
818 /* 1. Enable max PLL. */
819 reg_set16(LANE_CFG1_ADDR(PCIE) + COMPHY_SD_ADDR,
Pali Rohárc9ae2362021-03-24 16:40:46 +0100820 USE_MAX_PLL_RATE_EN, USE_MAX_PLL_RATE_EN);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300821
822 /* 2. Select 20 bit SERDES interface. */
823 reg_set16(GLOB_CLK_SRC_LO_ADDR(PCIE) + COMPHY_SD_ADDR,
Pali Rohárc9ae2362021-03-24 16:40:46 +0100824 CFG_SEL_20B, CFG_SEL_20B);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300825
826 /* 3. Force to use reg setting for PCIe mode */
827 reg_set16(MISC_REG1_ADDR(PCIE) + COMPHY_SD_ADDR,
Pali Rohárc9ae2362021-03-24 16:40:46 +0100828 SEL_BITS_PCIE_FORCE, SEL_BITS_PCIE_FORCE);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300829
830 /* 4. Change RX wait */
831 reg_set16(PWR_MGM_TIM1_ADDR(PCIE) + COMPHY_SD_ADDR,
832 CFG_PM_RXDEN_WAIT_1_UNIT | CFG_PM_RXDLOZ_WAIT_12_UNIT,
833 (CFG_PM_OSCCLK_WAIT_MASK | CFG_PM_RXDEN_WAIT_MASK |
834 CFG_PM_RXDLOZ_WAIT_MASK));
835
836 /* 5. Enable idle sync */
837 reg_set16(UNIT_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
838 UNIT_CTRL_DEFAULT_VALUE | IDLE_SYNC_EN, REG_16_BIT_MASK);
839
840 /* 6. Enable the output of 100M/125M/500M clock */
841 reg_set16(MISC_REG0_ADDR(PCIE) + COMPHY_SD_ADDR,
Pali Rohárbcc4416b2021-03-24 17:03:43 +0100842 MISC_REG0_DEFAULT_VALUE | CLK500M_EN | TXDCLK_2X_SEL | CLK100M_125M_EN,
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300843 REG_16_BIT_MASK);
844
845 /*
846 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in
847 * PCI-E driver
848 */
849
850 /*
851 * 8. Check crystal jumper setting and program the Power and PLL
852 * Control accordingly
853 */
854
855 if (get_ref_clk() == 40)
856 ref_clk = REF_CLOCK_SPEED_40M;
857 else
858 ref_clk = PCIE_REF_CLOCK_SPEED_25M;
859
860 reg_set16(PWR_PLL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
861 (PU_IVREF_BIT | PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT |
862 PU_TX_INTP_BIT | PU_DFE_BIT | ref_clk | PHY_MODE_PCIE),
863 REG_16_BIT_MASK);
864
865 /* 9. Override Speed_PLL value and use MAC PLL */
866 reg_set16(KVCO_CAL_CTRL_ADDR(PCIE) + COMPHY_SD_ADDR,
867 SPEED_PLL_VALUE_16 | USE_MAX_PLL_RATE_BIT, REG_16_BIT_MASK);
868
869 /* 10. Check the Polarity invert bit */
Pali Rohár741f7d62021-03-24 16:34:45 +0100870 data = 0U;
871 if (invert & COMPHY_POLARITY_TXD_INVERT) {
872 data |= TXD_INVERT_BIT;
873 }
874 if (invert & COMPHY_POLARITY_RXD_INVERT) {
875 data |= RXD_INVERT_BIT;
876 }
877 mask = TXD_INVERT_BIT | RXD_INVERT_BIT;
878 reg_set16(SYNC_PATTERN_REG_ADDR(PCIE) + COMPHY_SD_ADDR, data, mask);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300879
880 /* 11. Release SW reset */
881 reg_set16(GLOB_PHY_CTRL0_ADDR(PCIE) + COMPHY_SD_ADDR,
882 MODE_CORE_CLK_FREQ_SEL | MODE_PIPE_WIDTH_32,
883 SOFT_RESET | MODE_REFDIV);
884
885 /* Wait for > 55 us to allow PCLK be enabled */
886 udelay(PLL_SET_DELAY_US);
887
888 ret = polling_with_timeout(LANE_STATUS1_ADDR(PCIE) + COMPHY_SD_ADDR,
889 TXDCLK_PCLK_EN, TXDCLK_PCLK_EN,
890 COMPHY_PLL_TIMEOUT, REG_16BIT);
Pali Rohár26a98622021-09-23 14:47:18 +0200891 if (ret) {
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300892 ERROR("Failed to lock PCIE PLL\n");
Pali Rohár26a98622021-09-23 14:47:18 +0200893 return -ETIMEDOUT;
894 }
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300895
896 debug_exit();
897
Pali Rohár26a98622021-09-23 14:47:18 +0200898 return 0;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300899}
900
901int mvebu_3700_comphy_power_on(uint8_t comphy_index, uint32_t comphy_mode)
902{
903 int mode = COMPHY_GET_MODE(comphy_mode);
904 int ret = 0;
905
906 debug_enter();
907
908 switch (mode) {
909 case(COMPHY_SATA_MODE):
910 ret = mvebu_a3700_comphy_sata_power_on(comphy_index,
911 comphy_mode);
912 break;
913 case(COMPHY_SGMII_MODE):
Pali Rohár51974d22021-08-27 11:16:43 +0200914 case(COMPHY_2500BASEX_MODE):
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300915 ret = mvebu_a3700_comphy_sgmii_power_on(comphy_index,
916 comphy_mode);
917 break;
918 case (COMPHY_USB3_MODE):
919 case (COMPHY_USB3H_MODE):
920 ret = mvebu_a3700_comphy_usb3_power_on(comphy_index,
921 comphy_mode);
922 break;
923 case (COMPHY_PCIE_MODE):
924 ret = mvebu_a3700_comphy_pcie_power_on(comphy_index,
925 comphy_mode);
926 break;
927 default:
928 ERROR("comphy%d: unsupported comphy mode\n", comphy_index);
929 ret = -EINVAL;
930 break;
931 }
932
933 debug_exit();
934
935 return ret;
936}
937
938static int mvebu_a3700_comphy_usb3_power_off(void)
939{
940 /*
941 * Currently the USB3 MAC will control the USB3 PHY to set it to low
942 * state, thus do not need to power off USB3 PHY again.
943 */
944 debug_enter();
945 debug_exit();
946
947 return 0;
948}
949
Pali Rohár754cec92021-09-23 12:33:42 +0200950static int mvebu_a3700_comphy_sata_power_off(void)
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300951{
952 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300953 uint32_t offset;
954
955 debug_enter();
956
957 /* Set phy isolation mode */
958 offset = COMPHY_ISOLATION_CTRL_REG + SATAPHY_LANE2_REG_BASE_OFFSET;
Pali Rohár15b183c2021-09-23 14:11:25 +0200959 comphy_sata_set_indirect(comphy_indir_regs, offset, PHY_ISOLATE_MODE,
960 PHY_ISOLATE_MODE);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300961
962 /* Power off PLL, Tx, Rx */
963 offset = COMPHY_POWER_PLL_CTRL + SATAPHY_LANE2_REG_BASE_OFFSET;
Pali Rohár15b183c2021-09-23 14:11:25 +0200964 comphy_sata_set_indirect(comphy_indir_regs, offset, 0,
965 PU_PLL_BIT | PU_RX_BIT | PU_TX_BIT);
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300966
967 debug_exit();
968
969 return 0;
970}
971
972int mvebu_3700_comphy_power_off(uint8_t comphy_index, uint32_t comphy_mode)
973{
974 int mode = COMPHY_GET_MODE(comphy_mode);
975 int err = 0;
976
977 debug_enter();
978
Marek Behún4f94cbc2019-11-05 15:21:54 +0100979 if (!mode) {
980 /*
981 * The user did not specify which mode should be powered off.
982 * In this case we can identify this by reading the phy selector
983 * register.
984 */
985 mode = mvebu_a3700_comphy_get_mode(comphy_index);
986 }
987
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300988 switch (mode) {
Marek Behún4f94cbc2019-11-05 15:21:54 +0100989 case(COMPHY_SGMII_MODE):
Pali Rohár51974d22021-08-27 11:16:43 +0200990 case(COMPHY_2500BASEX_MODE):
Marek Behún4f94cbc2019-11-05 15:21:54 +0100991 err = mvebu_a3700_comphy_sgmii_power_off(comphy_index);
992 break;
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300993 case (COMPHY_USB3_MODE):
994 case (COMPHY_USB3H_MODE):
995 err = mvebu_a3700_comphy_usb3_power_off();
996 break;
997 case (COMPHY_SATA_MODE):
Pali Rohár754cec92021-09-23 12:33:42 +0200998 err = mvebu_a3700_comphy_sata_power_off();
Konstantin Porotchkinede192d2018-10-08 16:48:52 +0300999 break;
1000
1001 default:
1002 debug("comphy%d: power off is not implemented for mode %d\n",
1003 comphy_index, mode);
1004 break;
1005 }
1006
1007 debug_exit();
1008
1009 return err;
1010}
1011
1012static int mvebu_a3700_comphy_sata_is_pll_locked(void)
1013{
1014 uint32_t data, addr;
1015 uintptr_t comphy_indir_regs = COMPHY_INDIRECT_REG;
1016 int ret = 0;
1017
1018 debug_enter();
1019
1020 /* Polling status */
1021 mmio_write_32(comphy_indir_regs + COMPHY_LANE2_INDIR_ADDR_OFFSET,
1022 COMPHY_LOOPBACK_REG0 + SATAPHY_LANE2_REG_BASE_OFFSET);
1023 addr = comphy_indir_regs + COMPHY_LANE2_INDIR_DATA_OFFSET;
1024 data = polling_with_timeout(addr, PLL_READY_TX_BIT, PLL_READY_TX_BIT,
1025 COMPHY_PLL_TIMEOUT, REG_32BIT);
1026
1027 if (data != 0) {
1028 ERROR("TX PLL is not locked\n");
1029 ret = -ETIMEDOUT;
1030 }
1031
1032 debug_exit();
1033
1034 return ret;
1035}
1036
1037int mvebu_3700_comphy_is_pll_locked(uint8_t comphy_index, uint32_t comphy_mode)
1038{
1039 int mode = COMPHY_GET_MODE(comphy_mode);
1040 int ret = 0;
1041
1042 debug_enter();
1043
1044 switch (mode) {
1045 case(COMPHY_SATA_MODE):
1046 ret = mvebu_a3700_comphy_sata_is_pll_locked();
1047 break;
1048
1049 default:
1050 ERROR("comphy[%d] mode[%d] doesn't support PLL lock check\n",
1051 comphy_index, mode);
1052 ret = -EINVAL;
1053 break;
1054 }
1055
1056 debug_exit();
1057
1058 return ret;
1059}