blob: a85d95682014897ff9ad3d5620011d27b7dea53e [file] [log] [blame]
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +01001/*
Arvind Ram Prakash5b27ecf2023-06-23 14:47:30 -05002 * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <cpu_macros.S>
10#include <neoverse_n2.h>
Bipin Ravi86499742022-01-18 01:59:06 -060011#include "wa_cve_2022_23960_bhb_vector.S"
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +010012
13/* Hardware handled coherency */
14#if HW_ASSISTED_COHERENCY == 0
15#error "Neoverse N2 must be compiled with HW_ASSISTED_COHERENCY enabled"
16#endif
17
18/* 64-bit only core */
19#if CTX_INCLUDE_AARCH32_REGS == 1
20#error "Neoverse-N2 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
21#endif
22
Bipin Ravi86499742022-01-18 01:59:06 -060023#if WORKAROUND_CVE_2022_23960
24 wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
25#endif /* WORKAROUND_CVE_2022_23960 */
26
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050027/*
28 * ERRATA_DSU_2313941:
29 * The errata is defined in dsu_helpers.S and applies to Neoverse N2.
30 * Henceforth creating symbolic names to the already existing errata
31 * workaround functions to get them registered under the Errata Framework.
nayanpatel-arm277581e2021-08-06 17:46:10 -070032 */
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050033.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941
34.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa
35add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
nayanpatel-arm277581e2021-08-06 17:46:10 -070036
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050037workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655
nayanpatel-arm277581e2021-08-06 17:46:10 -070038 /* Apply instruction patching sequence */
39 ldr x0,=0x6
40 msr S3_6_c15_c8_0,x0
41 ldr x0,=0xF3A08002
42 msr S3_6_c15_c8_2,x0
43 ldr x0,=0xFFF0F7FE
44 msr S3_6_c15_c8_3,x0
45 ldr x0,=0x40000001003ff
46 msr S3_6_c15_c8_1,x0
47 ldr x0,=0x7
48 msr S3_6_c15_c8_0,x0
49 ldr x0,=0xBF200000
50 msr S3_6_c15_c8_2,x0
51 ldr x0,=0xFFEF0000
52 msr S3_6_c15_c8_3,x0
53 ldr x0,=0x40000001003f3
54 msr S3_6_c15_c8_1,x0
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050055workaround_reset_end neoverse_n2, ERRATUM(2002655)
nayanpatel-arm277581e2021-08-06 17:46:10 -070056
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050057check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0)
nayanpatel-arm277581e2021-08-06 17:46:10 -070058
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050059workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
Arvind Ram Prakash05464d92023-06-27 09:54:23 -050060 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050061workaround_reset_end neoverse_n2, ERRATUM(2025414)
Bipin Ravi7f565472021-03-31 10:10:27 -050062
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050063check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
Bipin Ravi7f565472021-03-31 10:10:27 -050064
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050065workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
Arvind Ram Prakash05464d92023-06-27 09:54:23 -050066 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050067workaround_reset_end neoverse_n2, ERRATUM(2067956)
Bipin Ravi7e030692021-08-30 13:02:51 -050068
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050069check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
Arvind Ram Prakash5b27ecf2023-06-23 14:47:30 -050070
Bipin Ravidd5bc632023-08-29 13:59:09 -050071workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
72 /* Stash ERRSELR_EL1 in x2 */
73 mrs x2, ERRSELR_EL1
74
75 /* Select error record 0 and clear ED bit */
76 msr ERRSELR_EL1, xzr
77 mrs x1, ERXCTLR_EL1
78 bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
79 msr ERXCTLR_EL1, x1
80
81 /* Restore ERRSELR_EL1 from x2 */
82 msr ERRSELR_EL1, x2
83workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB
84
85check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0)
86
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050087workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
Arvind Ram Prakash5b27ecf2023-06-23 14:47:30 -050088 /* Apply instruction patching sequence */
89 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
90 mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
91 bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
92 msr NEOVERSE_N2_CPUECTLR2_EL1, x1
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050093workaround_reset_end neoverse_n2, ERRATUM(2138953)
Bipin Ravi7e030692021-08-30 13:02:51 -050094
Arvind Ram Prakashf99b7982023-06-29 16:17:23 -050095check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3)
Bipin Ravi0ba631c2021-09-01 01:36:43 -050096
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -050097workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956
Bipin Ravi0ba631c2021-09-01 01:36:43 -050098 /* Apply instruction patching sequence */
99 ldr x0,=0x3
100 msr S3_6_c15_c8_0,x0
101 ldr x0,=0xF3A08002
102 msr S3_6_c15_c8_2,x0
103 ldr x0,=0xFFF0F7FE
104 msr S3_6_c15_c8_3,x0
105 ldr x0,=0x10002001003FF
106 msr S3_6_c15_c8_1,x0
107 ldr x0,=0x4
108 msr S3_6_c15_c8_0,x0
109 ldr x0,=0xBF200000
110 msr S3_6_c15_c8_2,x0
111 ldr x0,=0xFFEF0000
112 msr S3_6_c15_c8_3,x0
113 ldr x0,=0x10002001003F3
114 msr S3_6_c15_c8_1,x0
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500115workaround_reset_end neoverse_n2, ERRATUM(2138956)
Bipin Ravi0ba631c2021-09-01 01:36:43 -0500116
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500117check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0)
Bipin Ravi0ba631c2021-09-01 01:36:43 -0500118
nayanpatel-arm2f153992021-10-06 15:31:24 -0700119
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500120workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958
nayanpatel-arm2f153992021-10-06 15:31:24 -0700121 /* Apply instruction patching sequence */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500122 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500123workaround_reset_end neoverse_n2, ERRATUM(2138958)
nayanpatel-arm2f153992021-10-06 15:31:24 -0700124
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500125check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0)
nayanpatel-arm2f153992021-10-06 15:31:24 -0700126
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500127workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500128 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500129workaround_reset_end neoverse_n2, ERRATUM(2189731)
nayanpatel-armd4c5f9c2021-09-28 09:46:45 -0700130
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500131check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0)
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700132
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500133workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700134 /* Apply instruction patching sequence */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500135 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
Arvind Ram Prakash5b27ecf2023-06-23 14:47:30 -0500136 ldr x0, =0x2
137 msr S3_6_c15_c8_0, x0
138 ldr x0, =0x10F600E000
139 msr S3_6_c15_c8_2, x0
140 ldr x0, =0x10FF80E000
141 msr S3_6_c15_c8_3, x0
142 ldr x0, =0x80000000003FF
143 msr S3_6_c15_c8_1, x0
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500144workaround_reset_end neoverse_n2, ERRATUM(2242400)
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700145
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500146check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0)
nayanpatel-arm8e1aa012021-10-20 18:28:58 -0700147
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500148workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500149 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500150workaround_reset_end neoverse_n2, ERRATUM(2242415)
nayanpatel-armfed98132021-10-07 17:59:33 -0700151
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500152check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0)
nayanpatel-armfed98132021-10-07 17:59:33 -0700153
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500154workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757
nayanpatel-arm45b9f6f2021-10-20 17:30:46 -0700155 /* Apply instruction patching sequence */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500156 sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500157workaround_reset_end neoverse_n2, ERRATUM(2280757)
nayanpatel-arm45b9f6f2021-10-20 17:30:46 -0700158
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500159check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0)
Boyan Karatotevd3f8b4d2022-10-03 14:07:08 +0100160
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500161workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
Boyan Karatotevd3f8b4d2022-10-03 14:07:08 +0100162 /* Set bit 36 in ACTLR2_EL1 */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500163 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500164workaround_runtime_end neoverse_n2, ERRATUM(2326639)
Akram Ahmadb621bda2022-07-18 12:27:29 +0100165
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500166check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0)
Akram Ahmadb621bda2022-07-18 12:27:29 +0100167
Bipin Ravi2997ab92023-10-17 06:21:15 -0500168workaround_runtime_start neoverse_n2, ERRATUM(2340933), ERRATA_N2_2340933
169 /* Set bit 61 in CPUACTLR5_EL1 */
170 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, BIT(61)
171workaround_runtime_end neoverse_n2, ERRATUM(2340933)
172
173check_erratum_ls neoverse_n2, ERRATUM(2340933), CPU_REV(0, 0)
174
Bipin Ravi03ba5d82023-10-17 05:56:01 -0500175workaround_runtime_start neoverse_n2, ERRATUM(2346952), ERRATA_N2_2346952
176 /* Set TXREQ to STATIC and full L2 TQ size */
177 mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
178 mov x0, #CPUECTLR2_EL1_TXREQ_STATIC_FULL
179 bfi x1, x0, #CPUECTLR2_EL1_TXREQ_LSB, #CPUECTLR2_EL1_TXREQ_WIDTH
180 msr NEOVERSE_N2_CPUECTLR2_EL1, x1
181workaround_runtime_end neoverse_n2, ERRATUM(2346952)
182
183check_erratum_ls neoverse_n2, ERRATUM(2346952), CPU_REV(0, 2)
184
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500185workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738
Akram Ahmadb621bda2022-07-18 12:27:29 +0100186 /* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM
187 * ST to behave like PLD/PFRM LD and not cause
188 * invalidations to other PE caches.
189 */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500190 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500191workaround_reset_end neoverse_n2, ERRATUM(2376738)
Akram Ahmadb621bda2022-07-18 12:27:29 +0100192
Arvind Ram Prakashf99b7982023-06-29 16:17:23 -0500193check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3)
Daniel Boulby1af2b112022-07-06 14:33:13 +0100194
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500195workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450
Daniel Boulby1af2b112022-07-06 14:33:13 +0100196 /*Set bit 40 in ACTLR2_EL1 */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500197 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500198workaround_reset_end neoverse_n2, ERRATUM(2388450)
Daniel Boulby1af2b112022-07-06 14:33:13 +0100199
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500200check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0)
Daniel Boulby1af2b112022-07-06 14:33:13 +0100201
Arvind Ram Prakash465f93b2023-07-05 17:24:23 -0500202workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014
203 /* Set CPUACTLR5_EL1[56:55] to 2'b01 */
204 sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55
205 sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56
206workaround_reset_end neoverse_n2, ERRATUM(2743014)
207
208check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2)
209
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500210workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
Bipin Ravicc744bf2022-12-07 17:01:26 -0600211 /* dsb before isb of power down sequence */
212 dsb sy
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500213workaround_runtime_end neoverse_n2, ERRATUM(2743089)
Bipin Ravicc744bf2022-12-07 17:01:26 -0600214
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500215check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2)
Bipin Ravicc744bf2022-12-07 17:01:26 -0600216
Arvind Ram Prakash189622a2023-07-17 14:46:14 -0500217workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511
218 /* Set bit 47 in ACTLR3_EL1 */
219 sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47
220workaround_reset_end neoverse_n2, ERRATUM(2779511)
221
222check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
223
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500224workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
225#if IMAGE_BL31
226 /*
227 * The Neoverse-N2 generic vectors are overridden to apply errata
228 * mitigation on exception entry from lower ELs.
229 */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500230 override_vector_table wa_cve_vbar_neoverse_n2
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500231#endif /* IMAGE_BL31 */
232workaround_reset_end neoverse_n2, CVE(2022,23960)
233
234check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
Bipin Ravi86499742022-01-18 01:59:06 -0600235
Bipin Ravi7f565472021-03-31 10:10:27 -0500236 /* -------------------------------------------
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100237 * The CPU Ops reset function for Neoverse N2.
Bipin Ravi7f565472021-03-31 10:10:27 -0500238 * -------------------------------------------
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100239 */
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500240cpu_reset_func_start neoverse_n2
nayanpatel-arm277581e2021-08-06 17:46:10 -0700241
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100242 /* Check if the PE implements SSBS */
243 mrs x0, id_aa64pfr1_el1
244 tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
245 b.eq 1f
246
247 /* Disable speculative loads */
248 msr SSBS, xzr
2491:
250 /* Force all cacheable atomic instructions to be near */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500251 sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100252
Andre Przywara0b7f1b02023-03-21 13:53:19 +0000253#if ENABLE_FEAT_AMU
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100254 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
Thomas Abraham2be4a682023-12-10 14:15:44 +0000255 sysreg_bit_clear cptr_el3, TAM_BIT
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100256 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */
Thomas Abraham2be4a682023-12-10 14:15:44 +0000257 sysreg_bit_clear cptr_el2, TAM_BIT
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100258 /* No need to enable the counters as this would be done at el3 exit */
259#endif
260
261#if NEOVERSE_Nx_EXTERNAL_LLC
262 /* Some systems may have External LLC, core needs to be made aware */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500263 sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100264#endif
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500265cpu_reset_func_end neoverse_n2
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100266
267func neoverse_n2_core_pwr_dwn
Boyan Karatotevd3f8b4d2022-10-03 14:07:08 +0100268
Bipin Ravidd5bc632023-08-29 13:59:09 -0500269 apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
270 apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
271
Bipin Ravi7f565472021-03-31 10:10:27 -0500272 /* ---------------------------------------------------
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100273 * Enable CPU power down bit in power control register
274 * No need to do cache maintenance here.
Bipin Ravi7f565472021-03-31 10:10:27 -0500275 * ---------------------------------------------------
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100276 */
Arvind Ram Prakash05464d92023-06-27 09:54:23 -0500277 sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT
278
279 apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
280
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100281 isb
282 ret
283endfunc neoverse_n2_core_pwr_dwn
284
Arvind Ram Prakash7aea56c2023-06-26 15:05:40 -0500285errata_report_shim neoverse_n2
Javier Almansa Sobrino9faad3c2020-10-23 13:22:07 +0100286
287 /* ---------------------------------------------
288 * This function provides Neoverse N2 specific
289 * register information for crash reporting.
290 * It needs to return with x6 pointing to
291 * a list of register names in ASCII and
292 * x8 - x15 having values of registers to be
293 * reported.
294 * ---------------------------------------------
295 */
296.section .rodata.neoverse_n2_regs, "aS"
297neoverse_n2_regs: /* The ASCII list of register names to be reported */
298 .asciz "cpupwrctlr_el1", ""
299
300func neoverse_n2_cpu_reg_dump
301 adr x6, neoverse_n2_regs
302 mrs x8, NEOVERSE_N2_CPUPWRCTLR_EL1
303 ret
304endfunc neoverse_n2_cpu_reg_dump
305
306declare_cpu_ops neoverse_n2, NEOVERSE_N2_MIDR, \
307 neoverse_n2_reset_func, \
308 neoverse_n2_core_pwr_dwn