| commit | 2be4a68ae7eb41f72967208a7b34b5a7529b34bc | [log] [tgz] |
|---|---|---|
| author | Thomas Abraham <thomas.abraham@arm.com> | Sun Dec 10 14:15:44 2023 +0000 |
| committer | Thomas Abraham <thomas.abraham@arm.com> | Sun Dec 10 17:01:44 2023 +0000 |
| tree | 4b18cd01967d20fc848768e5da691f08d798adc1 | |
| parent | 9b9e0acdda5545580eeecc786bd3eb421ee3b7a0 [diff] |
fix(cpus): fix incorrect AMU trap settings for N2 CPU The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset handling sequence of the Neoverse N2 CPU. As these bits are set, any access of AMU registers from EL0/EL1 and EL2 respectively are incorrectly trapped to a higher EL. Fix this by clearing the TAM bits in both the CPTR_EL2 and CPTR_EL3 registers. Signed-off-by: Thomas Abraham <thomas.abraham@arm.com> Change-Id: I357b16dfc7d7367b8a0c8086faac28f3e2866cd8