fix(cpus): fix incorrect AMU trap settings for N2 CPU
The TAM bits of CPTR_EL2 and CPTR_EL3 are incorrectly set in the reset
handling sequence of the Neoverse N2 CPU. As these bits are set, any
access of AMU registers from EL0/EL1 and EL2 respectively are
incorrectly trapped to a higher EL. Fix this by clearing the TAM bits in
both the CPTR_EL2 and CPTR_EL3 registers.
Signed-off-by: Thomas Abraham <thomas.abraham@arm.com>
Change-Id: I357b16dfc7d7367b8a0c8086faac28f3e2866cd8
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 477522f..a85d956 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -252,9 +252,9 @@
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- sysreg_bit_set cptr_el3, TAM_BIT
+ sysreg_bit_clear cptr_el3, TAM_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
- sysreg_bit_set cptr_el2, TAM_BIT
+ sysreg_bit_clear cptr_el2, TAM_BIT
/* No need to enable the counters as this would be done at el3 exit */
#endif