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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Deepika Bhavnani79ffab52019-08-27 00:32:24 +03002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +01007#ifndef PSCI_PRIVATE_H
8#define PSCI_PRIVATE_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <stdbool.h>
11
Achin Guptaa59caa42013-12-05 14:21:04 +000012#include <arch.h>
Antonio Nino Diazdd0e85c2018-07-17 09:51:33 +010013#include <arch_helpers.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <common/bl_common.h>
15#include <lib/bakery_lock.h>
16#include <lib/el3_runtime/cpu_data.h>
17#include <lib/psci/psci.h>
18#include <lib/spinlock.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
Soby Mathew6cdddaf2015-01-07 11:10:22 +000020/*
21 * The PSCI capability which are provided by the generic code but does not
22 * depend on the platform or spd capabilities.
23 */
24#define PSCI_GENERIC_CAP \
25 (define_psci_cap(PSCI_VERSION) | \
26 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \
27 define_psci_cap(PSCI_FEATURES))
28
29/*
30 * The PSCI capabilities mask for 64 bit functions.
31 */
32#define PSCI_CAP_64BIT_MASK \
33 (define_psci_cap(PSCI_CPU_SUSPEND_AARCH64) | \
34 define_psci_cap(PSCI_CPU_ON_AARCH64) | \
35 define_psci_cap(PSCI_AFFINITY_INFO_AARCH64) | \
36 define_psci_cap(PSCI_MIG_AARCH64) | \
Soby Mathew96168382014-12-17 14:47:57 +000037 define_psci_cap(PSCI_MIG_INFO_UP_CPU_AARCH64) | \
Jeenu Viswambharan7f03e9d92016-08-03 15:54:50 +010038 define_psci_cap(PSCI_NODE_HW_STATE_AARCH64) | \
Yatharth Kochar241ec6c2016-05-09 18:26:35 +010039 define_psci_cap(PSCI_SYSTEM_SUSPEND_AARCH64) | \
40 define_psci_cap(PSCI_STAT_RESIDENCY_AARCH64) | \
Roberto Vargasb820ad02017-07-26 09:23:09 +010041 define_psci_cap(PSCI_STAT_COUNT_AARCH64) | \
Roberto Vargas653fb8f2017-10-12 10:57:40 +010042 define_psci_cap(PSCI_SYSTEM_RESET2_AARCH64) | \
43 define_psci_cap(PSCI_MEM_CHK_RANGE_AARCH64))
Soby Mathew6cdddaf2015-01-07 11:10:22 +000044
Soby Mathew981487a2015-07-13 14:10:57 +010045/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010046 * Helper functions to get/set the fields of PSCI per-cpu data.
Soby Mathew981487a2015-07-13 14:10:57 +010047 */
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010048static inline void psci_set_aff_info_state(aff_info_state_t aff_state)
49{
50 set_cpu_data(psci_svc_cpu_data.aff_info_state, aff_state);
51}
Soby Mathew981487a2015-07-13 14:10:57 +010052
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010053static inline aff_info_state_t psci_get_aff_info_state(void)
54{
55 return get_cpu_data(psci_svc_cpu_data.aff_info_state);
56}
57
Deepika Bhavnani79ffab52019-08-27 00:32:24 +030058static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx)
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010059{
Deepika Bhavnani79ffab52019-08-27 00:32:24 +030060 return get_cpu_data_by_index(idx,
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010061 psci_svc_cpu_data.aff_info_state);
62}
63
Deepika Bhavnani79ffab52019-08-27 00:32:24 +030064static inline void psci_set_aff_info_state_by_idx(unsigned int idx,
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010065 aff_info_state_t aff_state)
66{
Deepika Bhavnani79ffab52019-08-27 00:32:24 +030067 set_cpu_data_by_index(idx,
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010068 psci_svc_cpu_data.aff_info_state, aff_state);
69}
70
71static inline unsigned int psci_get_suspend_pwrlvl(void)
72{
73 return get_cpu_data(psci_svc_cpu_data.target_pwrlvl);
74}
Soby Mathew981487a2015-07-13 14:10:57 +010075
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010076static inline void psci_set_suspend_pwrlvl(unsigned int target_lvl)
77{
78 set_cpu_data(psci_svc_cpu_data.target_pwrlvl, target_lvl);
79}
80
81static inline void psci_set_cpu_local_state(plat_local_state_t state)
82{
83 set_cpu_data(psci_svc_cpu_data.local_state, state);
84}
85
86static inline plat_local_state_t psci_get_cpu_local_state(void)
87{
88 return get_cpu_data(psci_svc_cpu_data.local_state);
89}
90
Deepika Bhavnani79ffab52019-08-27 00:32:24 +030091static inline plat_local_state_t psci_get_cpu_local_state_by_idx(
92 unsigned int idx)
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010093{
Deepika Bhavnani79ffab52019-08-27 00:32:24 +030094 return get_cpu_data_by_index(idx,
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010095 psci_svc_cpu_data.local_state);
96}
97
98/* Helper function to identify a CPU standby request in PSCI Suspend call */
Antonio Nino Diazde11a5b2018-08-01 16:42:10 +010099static inline bool is_cpu_standby_req(unsigned int is_power_down_state,
100 unsigned int retn_lvl)
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100101{
Antonio Nino Diazde11a5b2018-08-01 16:42:10 +0100102 return (is_power_down_state == 0U) && (retn_lvl == 0U);
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100103}
Soby Mathew6cdddaf2015-01-07 11:10:22 +0000104
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105/*******************************************************************************
Soby Mathew981487a2015-07-13 14:10:57 +0100106 * The following two data structures implement the power domain tree. The tree
107 * is used to track the state of all the nodes i.e. power domain instances
108 * described by the platform. The tree consists of nodes that describe CPU power
109 * domains i.e. leaf nodes and all other power domains which are parents of a
110 * CPU power domain i.e. non-leaf nodes.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100111 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100112typedef struct non_cpu_pwr_domain_node {
113 /*
114 * Index of the first CPU power domain node level 0 which has this node
115 * as its parent.
116 */
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300117 unsigned int cpu_start_idx;
Soby Mathew981487a2015-07-13 14:10:57 +0100118
119 /*
120 * Number of CPU power domains which are siblings of the domain indexed
121 * by 'cpu_start_idx' i.e. all the domains in the range 'cpu_start_idx
122 * -> cpu_start_idx + ncpus' have this node as their parent.
123 */
124 unsigned int ncpus;
125
126 /*
127 * Index of the parent power domain node.
128 * TODO: Figure out whether to whether using pointer is more efficient.
129 */
130 unsigned int parent_node;
131
132 plat_local_state_t local_state;
133
Achin Gupta75f73672013-12-05 16:33:10 +0000134 unsigned char level;
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100135
136 /* For indexing the psci_lock array*/
Soby Mathew981487a2015-07-13 14:10:57 +0100137 unsigned char lock_index;
Soby Mathew981487a2015-07-13 14:10:57 +0100138} non_cpu_pd_node_t;
139
140typedef struct cpu_pwr_domain_node {
Soby Mathew011ca182015-07-29 17:05:03 +0100141 u_register_t mpidr;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100142
Soby Mathew981487a2015-07-13 14:10:57 +0100143 /*
144 * Index of the parent power domain node.
145 * TODO: Figure out whether to whether using pointer is more efficient.
146 */
147 unsigned int parent_node;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148
Soby Mathew981487a2015-07-13 14:10:57 +0100149 /*
150 * A CPU power domain does not require state coordination like its
151 * parent power domains. Hence this node does not include a bakery
152 * lock. A spinlock is required by the CPU_ON handler to prevent a race
153 * when multiple CPUs try to turn ON the same target CPU.
154 */
155 spinlock_t cpu_lock;
156} cpu_pd_node_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100157
158/*******************************************************************************
Antonio Nino Diazdd0e85c2018-07-17 09:51:33 +0100159 * The following are helpers and declarations of locks.
160 ******************************************************************************/
161#if HW_ASSISTED_COHERENCY
162/*
163 * On systems where participant CPUs are cache-coherent, we can use spinlocks
164 * instead of bakery locks.
165 */
166#define DEFINE_PSCI_LOCK(_name) spinlock_t _name
167#define DECLARE_PSCI_LOCK(_name) extern DEFINE_PSCI_LOCK(_name)
168
169/* One lock is required per non-CPU power domain node */
170DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
171
172/*
173 * On systems with hardware-assisted coherency, make PSCI cache operations NOP,
174 * as PSCI participants are cache-coherent, and there's no need for explicit
175 * cache maintenance operations or barriers to coordinate their state.
176 */
177static inline void psci_flush_dcache_range(uintptr_t __unused addr,
178 size_t __unused size)
179{
180 /* Empty */
181}
182
183#define psci_flush_cpu_data(member)
184#define psci_inv_cpu_data(member)
185
186static inline void psci_dsbish(void)
187{
188 /* Empty */
189}
190
191static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node)
192{
193 spin_lock(&psci_locks[non_cpu_pd_node->lock_index]);
194}
195
196static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node)
197{
198 spin_unlock(&psci_locks[non_cpu_pd_node->lock_index]);
199}
200
201#else /* if HW_ASSISTED_COHERENCY == 0 */
202/*
203 * Use bakery locks for state coordination as not all PSCI participants are
204 * cache coherent.
205 */
206#define DEFINE_PSCI_LOCK(_name) DEFINE_BAKERY_LOCK(_name)
207#define DECLARE_PSCI_LOCK(_name) DECLARE_BAKERY_LOCK(_name)
208
209/* One lock is required per non-CPU power domain node */
210DECLARE_PSCI_LOCK(psci_locks[PSCI_NUM_NON_CPU_PWR_DOMAINS]);
211
212/*
213 * If not all PSCI participants are cache-coherent, perform cache maintenance
214 * and issue barriers wherever required to coordinate state.
215 */
216static inline void psci_flush_dcache_range(uintptr_t addr, size_t size)
217{
218 flush_dcache_range(addr, size);
219}
220
221#define psci_flush_cpu_data(member) flush_cpu_data(member)
222#define psci_inv_cpu_data(member) inv_cpu_data(member)
223
224static inline void psci_dsbish(void)
225{
226 dsbish();
227}
228
229static inline void psci_lock_get(non_cpu_pd_node_t *non_cpu_pd_node)
230{
231 bakery_lock_get(&psci_locks[non_cpu_pd_node->lock_index]);
232}
233
234static inline void psci_lock_release(non_cpu_pd_node_t *non_cpu_pd_node)
235{
236 bakery_lock_release(&psci_locks[non_cpu_pd_node->lock_index]);
237}
238
239#endif /* HW_ASSISTED_COHERENCY */
240
241static inline void psci_lock_init(non_cpu_pd_node_t *non_cpu_pd_node,
242 unsigned char idx)
243{
244 non_cpu_pd_node[idx].lock_index = idx;
245}
246
247/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100248 * Data prototypes
249 ******************************************************************************/
Soby Mathew981487a2015-07-13 14:10:57 +0100250extern const plat_psci_ops_t *psci_plat_pm_ops;
251extern non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
252extern cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
Soby Mathew011ca182015-07-29 17:05:03 +0100253extern unsigned int psci_caps;
Pankaj Gupta02c35682019-10-15 15:44:45 +0530254extern unsigned int psci_plat_core_count;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100255
256/*******************************************************************************
Jeenu Viswambharan7f366602014-02-20 17:11:00 +0000257 * SPD's power management hooks registered with PSCI
Achin Gupta607084e2014-02-09 18:24:19 +0000258 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100259extern const spd_pm_ops_t *psci_spd_pm;
Achin Gupta607084e2014-02-09 18:24:19 +0000260
261/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262 * Function prototypes
263 ******************************************************************************/
264/* Private exported functions from psci_common.c */
Soby Mathew981487a2015-07-13 14:10:57 +0100265int psci_validate_power_state(unsigned int power_state,
266 psci_power_state_t *state_info);
267void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100268int psci_validate_mpidr(u_register_t mpidr);
Soby Mathew981487a2015-07-13 14:10:57 +0100269void psci_init_req_local_pwr_states(void);
Achin Gupta9b2bf252016-06-28 16:46:15 +0100270void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
271 psci_power_state_t *target_state);
Soby Mathewf1f97a12015-07-15 12:13:26 +0100272int psci_validate_entry_point(entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100273 uintptr_t entrypoint, u_register_t context_id);
Deepika Bhavnani79ffab52019-08-27 00:32:24 +0300274void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
Soby Mathew011ca182015-07-29 17:05:03 +0100275 unsigned int end_lvl,
Antonio Nino Diaz78a95a62018-07-17 15:10:08 +0100276 unsigned int *node_index);
Soby Mathew011ca182015-07-29 17:05:03 +0100277void psci_do_state_coordination(unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100278 psci_power_state_t *state_info);
Andrew F. Davis74e89782019-06-04 10:46:54 -0400279void psci_acquire_pwr_domain_locks(unsigned int end_pwrlvl,
280 const unsigned int *parent_nodes);
281void psci_release_pwr_domain_locks(unsigned int end_pwrlvl,
282 const unsigned int *parent_nodes);
Soby Mathew981487a2015-07-13 14:10:57 +0100283int psci_validate_suspend_req(const psci_power_state_t *state_info,
Roberto Vargas777dd432018-02-12 12:36:17 +0000284 unsigned int is_power_down_state);
Soby Mathew981487a2015-07-13 14:10:57 +0100285unsigned int psci_find_max_off_lvl(const psci_power_state_t *state_info);
286unsigned int psci_find_target_suspend_lvl(const psci_power_state_t *state_info);
Soby Mathew011ca182015-07-29 17:05:03 +0100287void psci_set_pwr_domains_to_run(unsigned int end_pwrlvl);
Soby Mathew981487a2015-07-13 14:10:57 +0100288void psci_print_power_domain_map(void);
Soby Mathew96168382014-12-17 14:47:57 +0000289unsigned int psci_is_last_on_cpu(void);
Soby Mathew011ca182015-07-29 17:05:03 +0100290int psci_spd_migrate_info(u_register_t *mpidr);
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000291void psci_do_pwrdown_sequence(unsigned int power_level);
292
293/*
294 * CPU power down is directly called only when HW_ASSISTED_COHERENCY is
295 * available. Otherwise, this needs post-call stack maintenance, which is
296 * handled in assembly.
297 */
298void prepare_cpu_pwr_dwn(unsigned int power_level);
Achin Gupta0959db52013-12-02 17:33:04 +0000299
Soby Mathew981487a2015-07-13 14:10:57 +0100300/* Private exported functions from psci_on.c */
Soby Mathewa0fedc42016-06-16 14:52:04 +0100301int psci_cpu_on_start(u_register_t target_cpu,
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100302 const entry_point_info_t *ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100303
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100304void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100305
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000306/* Private exported functions from psci_off.c */
Soby Mathew011ca182015-07-29 17:05:03 +0100307int psci_do_cpu_off(unsigned int end_pwrlvl);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100308
Sandrine Bailleuxf4119ec2015-12-17 13:58:58 +0000309/* Private exported functions from psci_suspend.c */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100310void psci_cpu_suspend_start(const entry_point_info_t *ep,
Soby Mathew011ca182015-07-29 17:05:03 +0100311 unsigned int end_pwrlvl,
Soby Mathew981487a2015-07-13 14:10:57 +0100312 psci_power_state_t *state_info,
Roberto Vargas777dd432018-02-12 12:36:17 +0000313 unsigned int is_power_down_state);
Soby Mathew8595b872015-01-06 15:36:38 +0000314
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100315void psci_cpu_suspend_finish(int cpu_idx, const psci_power_state_t *state_info);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000316
Achin Guptae1aa5162014-06-26 09:58:52 +0100317/* Private exported functions from psci_helpers.S */
Soby Mathew011ca182015-07-29 17:05:03 +0100318void psci_do_pwrdown_cache_maintenance(unsigned int pwr_level);
Achin Guptae1aa5162014-06-26 09:58:52 +0100319void psci_do_pwrup_cache_maintenance(void);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100320
Juan Castillo4dc4a472014-08-12 11:17:06 +0100321/* Private exported functions from psci_system_off.c */
322void __dead2 psci_system_off(void);
323void __dead2 psci_system_reset(void);
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100324u_register_t psci_system_reset2(uint32_t reset_type, u_register_t cookie);
Juan Castillo4dc4a472014-08-12 11:17:06 +0100325
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100326/* Private exported functions from psci_stat.c */
327void psci_stats_update_pwr_down(unsigned int end_pwrlvl,
328 const psci_power_state_t *state_info);
329void psci_stats_update_pwr_up(unsigned int end_pwrlvl,
dp-arm66abfbe2017-01-31 13:01:04 +0000330 const psci_power_state_t *state_info);
Yatharth Kochar241ec6c2016-05-09 18:26:35 +0100331u_register_t psci_stat_residency(u_register_t target_cpu,
332 unsigned int power_state);
333u_register_t psci_stat_count(u_register_t target_cpu,
334 unsigned int power_state);
335
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100336/* Private exported functions from psci_mem_protect.c */
Antonio Nino Diazf5c60012018-07-16 23:36:10 +0100337u_register_t psci_mem_protect(unsigned int enable);
338u_register_t psci_mem_chk_range(uintptr_t base, u_register_t length);
Roberto Vargas0a4c2612017-08-03 08:16:16 +0100339
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +0100340#endif /* PSCI_PRIVATE_H */