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Achin Gupta92712a52015-09-03 14:18:02 +01001/*
Jeenu Viswambharan24e70292017-09-22 08:32:09 +01002 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta92712a52015-09-03 14:18:02 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta92712a52015-09-03 14:18:02 +01005 */
6
7#include <arch.h>
8#include <arch_helpers.h>
9#include <assert.h>
10#include <debug.h>
11#include <gic_common.h>
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +010012#include <interrupt_props.h>
Soby Mathew50f6fe42016-02-01 17:59:22 +000013#include "../common/gic_common_private.h"
Achin Gupta92712a52015-09-03 14:18:02 +010014#include "gicv3_private.h"
15
16/*
17 * Accessor to read the GIC Distributor IGRPMODR corresponding to the
18 * interrupt `id`, 32 interrupt IDs at a time.
19 */
20unsigned int gicd_read_igrpmodr(uintptr_t base, unsigned int id)
21{
22 unsigned n = id >> IGRPMODR_SHIFT;
23 return mmio_read_32(base + GICD_IGRPMODR + (n << 2));
24}
25
26/*
27 * Accessor to write the GIC Distributor IGRPMODR corresponding to the
28 * interrupt `id`, 32 interrupt IDs at a time.
29 */
30void gicd_write_igrpmodr(uintptr_t base, unsigned int id, unsigned int val)
31{
32 unsigned n = id >> IGRPMODR_SHIFT;
33 mmio_write_32(base + GICD_IGRPMODR + (n << 2), val);
34}
35
36/*
37 * Accessor to get the bit corresponding to interrupt ID
38 * in GIC Distributor IGRPMODR.
39 */
40unsigned int gicd_get_igrpmodr(uintptr_t base, unsigned int id)
41{
42 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
43 unsigned int reg_val = gicd_read_igrpmodr(base, id);
44
45 return (reg_val >> bit_num) & 0x1;
46}
47
48/*
49 * Accessor to set the bit corresponding to interrupt ID
50 * in GIC Distributor IGRPMODR.
51 */
52void gicd_set_igrpmodr(uintptr_t base, unsigned int id)
53{
54 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
55 unsigned int reg_val = gicd_read_igrpmodr(base, id);
56
57 gicd_write_igrpmodr(base, id, reg_val | (1 << bit_num));
58}
59
60/*
61 * Accessor to clear the bit corresponding to interrupt ID
62 * in GIC Distributor IGRPMODR.
63 */
64void gicd_clr_igrpmodr(uintptr_t base, unsigned int id)
65{
66 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
67 unsigned int reg_val = gicd_read_igrpmodr(base, id);
68
69 gicd_write_igrpmodr(base, id, reg_val & ~(1 << bit_num));
70}
71
72/*
73 * Accessor to read the GIC Re-distributor IPRIORITYR corresponding to the
74 * interrupt `id`, 4 interrupts IDs at a time.
75 */
76unsigned int gicr_read_ipriorityr(uintptr_t base, unsigned int id)
77{
78 unsigned n = id >> IPRIORITYR_SHIFT;
79 return mmio_read_32(base + GICR_IPRIORITYR + (n << 2));
80}
81
82/*
83 * Accessor to write the GIC Re-distributor IPRIORITYR corresponding to the
84 * interrupt `id`, 4 interrupts IDs at a time.
85 */
86void gicr_write_ipriorityr(uintptr_t base, unsigned int id, unsigned int val)
87{
88 unsigned n = id >> IPRIORITYR_SHIFT;
89 mmio_write_32(base + GICR_IPRIORITYR + (n << 2), val);
90}
91
92/*
93 * Accessor to get the bit corresponding to interrupt ID
94 * from GIC Re-distributor IGROUPR0.
95 */
96unsigned int gicr_get_igroupr0(uintptr_t base, unsigned int id)
97{
98 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
99 unsigned int reg_val = gicr_read_igroupr0(base);
100
101 return (reg_val >> bit_num) & 0x1;
102}
103
104/*
105 * Accessor to set the bit corresponding to interrupt ID
106 * in GIC Re-distributor IGROUPR0.
107 */
108void gicr_set_igroupr0(uintptr_t base, unsigned int id)
109{
110 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
111 unsigned int reg_val = gicr_read_igroupr0(base);
112
113 gicr_write_igroupr0(base, reg_val | (1 << bit_num));
114}
115
116/*
117 * Accessor to clear the bit corresponding to interrupt ID
118 * in GIC Re-distributor IGROUPR0.
119 */
120void gicr_clr_igroupr0(uintptr_t base, unsigned int id)
121{
122 unsigned bit_num = id & ((1 << IGROUPR_SHIFT) - 1);
123 unsigned int reg_val = gicr_read_igroupr0(base);
124
125 gicr_write_igroupr0(base, reg_val & ~(1 << bit_num));
126}
127
128/*
129 * Accessor to get the bit corresponding to interrupt ID
130 * from GIC Re-distributor IGRPMODR0.
131 */
132unsigned int gicr_get_igrpmodr0(uintptr_t base, unsigned int id)
133{
134 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
135 unsigned int reg_val = gicr_read_igrpmodr0(base);
136
137 return (reg_val >> bit_num) & 0x1;
138}
139
140/*
141 * Accessor to set the bit corresponding to interrupt ID
142 * in GIC Re-distributor IGRPMODR0.
143 */
144void gicr_set_igrpmodr0(uintptr_t base, unsigned int id)
145{
146 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
147 unsigned int reg_val = gicr_read_igrpmodr0(base);
148
149 gicr_write_igrpmodr0(base, reg_val | (1 << bit_num));
150}
151
152/*
153 * Accessor to clear the bit corresponding to interrupt ID
154 * in GIC Re-distributor IGRPMODR0.
155 */
156void gicr_clr_igrpmodr0(uintptr_t base, unsigned int id)
157{
158 unsigned bit_num = id & ((1 << IGRPMODR_SHIFT) - 1);
159 unsigned int reg_val = gicr_read_igrpmodr0(base);
160
161 gicr_write_igrpmodr0(base, reg_val & ~(1 << bit_num));
162}
163
164/*
165 * Accessor to set the bit corresponding to interrupt ID
166 * in GIC Re-distributor ISENABLER0.
167 */
168void gicr_set_isenabler0(uintptr_t base, unsigned int id)
169{
170 unsigned bit_num = id & ((1 << ISENABLER_SHIFT) - 1);
171
172 gicr_write_isenabler0(base, (1 << bit_num));
173}
174
Soby Mathew421259e2016-01-15 14:20:57 +0000175/*
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100176 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
Jeenu Viswambharan0fcdfff2017-09-22 08:32:09 +0100177 * ICENABLER0.
178 */
179void gicr_set_icenabler0(uintptr_t base, unsigned int id)
180{
181 unsigned bit_num = id & ((1 << ICENABLER_SHIFT) - 1);
182
183 gicr_write_icenabler0(base, (1 << bit_num));
184}
185
186/*
187 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
Jeenu Viswambharan24e70292017-09-22 08:32:09 +0100188 * ISACTIVER0.
189 */
190unsigned int gicr_get_isactiver0(uintptr_t base, unsigned int id)
191{
192 unsigned bit_num = id & ((1 << ISACTIVER_SHIFT) - 1);
193 unsigned int reg_val = gicr_read_isactiver0(base);
194
195 return (reg_val >> bit_num) & 0x1;
196}
197
198/*
Jeenu Viswambharaneb1c12c2017-09-22 08:32:09 +0100199 * Accessor to clear the bit corresponding to interrupt ID in GIC Re-distributor
200 * ICPENDRR0.
201 */
202void gicr_set_icpendr0(uintptr_t base, unsigned int id)
203{
204 unsigned bit_num = id & ((1 << ICPENDR_SHIFT) - 1);
205
206 gicr_write_icpendr0(base, (1 << bit_num));
207}
208
209/*
210 * Accessor to set the bit corresponding to interrupt ID in GIC Re-distributor
211 * ISPENDR0.
212 */
213void gicr_set_ispendr0(uintptr_t base, unsigned int id)
214{
215 unsigned bit_num = id & ((1 << ISPENDR_SHIFT) - 1);
216
217 gicr_write_ispendr0(base, (1 << bit_num));
218}
219
220/*
Soby Mathew421259e2016-01-15 14:20:57 +0000221 * Accessor to set the byte corresponding to interrupt ID
222 * in GIC Re-distributor IPRIORITYR.
223 */
224void gicr_set_ipriorityr(uintptr_t base, unsigned int id, unsigned int pri)
225{
226 mmio_write_8(base + GICR_IPRIORITYR + id, pri & GIC_PRI_MASK);
227}
228
Jeenu Viswambharan4684bce2017-09-22 08:32:09 +0100229/*
230 * Accessor to set the bit fields corresponding to interrupt ID
231 * in GIC Re-distributor ICFGR0.
232 */
233void gicr_set_icfgr0(uintptr_t base, unsigned int id, unsigned int cfg)
234{
235 unsigned bit_num = id & ((1 << ICFGR_SHIFT) - 1);
236 uint32_t reg_val = gicr_read_icfgr0(base);
237
238 /* Clear the field, and insert required configuration */
239 reg_val &= ~(GIC_CFG_MASK << bit_num);
240 reg_val |= ((cfg & GIC_CFG_MASK) << bit_num);
241
242 gicr_write_icfgr0(base, reg_val);
243}
244
245/*
246 * Accessor to set the bit fields corresponding to interrupt ID
247 * in GIC Re-distributor ICFGR1.
248 */
249void gicr_set_icfgr1(uintptr_t base, unsigned int id, unsigned int cfg)
250{
251 unsigned bit_num = id & ((1 << ICFGR_SHIFT) - 1);
252 uint32_t reg_val = gicr_read_icfgr1(base);
253
254 /* Clear the field, and insert required configuration */
255 reg_val &= ~(GIC_CFG_MASK << bit_num);
256 reg_val |= ((cfg & GIC_CFG_MASK) << bit_num);
257
258 gicr_write_icfgr1(base, reg_val);
259}
260
Achin Gupta92712a52015-09-03 14:18:02 +0100261/******************************************************************************
262 * This function marks the core as awake in the re-distributor and
263 * ensures that the interface is active.
264 *****************************************************************************/
265void gicv3_rdistif_mark_core_awake(uintptr_t gicr_base)
266{
267 /*
268 * The WAKER_PS_BIT should be changed to 0
269 * only when WAKER_CA_BIT is 1.
270 */
271 assert(gicr_read_waker(gicr_base) & WAKER_CA_BIT);
272
273 /* Mark the connected core as awake */
274 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) & ~WAKER_PS_BIT);
275
276 /* Wait till the WAKER_CA_BIT changes to 0 */
277 while (gicr_read_waker(gicr_base) & WAKER_CA_BIT)
278 ;
279}
280
281
282/******************************************************************************
283 * This function marks the core as asleep in the re-distributor and ensures
284 * that the interface is quiescent.
285 *****************************************************************************/
286void gicv3_rdistif_mark_core_asleep(uintptr_t gicr_base)
287{
288 /* Mark the connected core as asleep */
289 gicr_write_waker(gicr_base, gicr_read_waker(gicr_base) | WAKER_PS_BIT);
290
291 /* Wait till the WAKER_CA_BIT changes to 1 */
292 while (!(gicr_read_waker(gicr_base) & WAKER_CA_BIT))
293 ;
294}
295
296
297/*******************************************************************************
298 * This function probes the Redistributor frames when the driver is initialised
299 * and saves their base addresses. These base addresses are used later to
300 * initialise each Redistributor interface.
301 ******************************************************************************/
302void gicv3_rdistif_base_addrs_probe(uintptr_t *rdistif_base_addrs,
303 unsigned int rdistif_num,
304 uintptr_t gicr_base,
305 mpidr_hash_fn mpidr_to_core_pos)
306{
Soby Mathewa0fedc42016-06-16 14:52:04 +0100307 u_register_t mpidr;
Achin Gupta92712a52015-09-03 14:18:02 +0100308 unsigned int proc_num;
309 unsigned long long typer_val;
310 uintptr_t rdistif_base = gicr_base;
311
312 assert(rdistif_base_addrs);
313
314 /*
315 * Iterate over the Redistributor frames. Store the base address of each
316 * frame in the platform provided array. Use the "Processor Number"
317 * field to index into the array if the platform has not provided a hash
318 * function to convert an MPIDR (obtained from the "Affinity Value"
319 * field into a linear index.
320 */
321 do {
322 typer_val = gicr_read_typer(rdistif_base);
323 if (mpidr_to_core_pos) {
324 mpidr = mpidr_from_gicr_typer(typer_val);
325 proc_num = mpidr_to_core_pos(mpidr);
326 } else {
327 proc_num = (typer_val >> TYPER_PROC_NUM_SHIFT) &
328 TYPER_PROC_NUM_MASK;
329 }
330 assert(proc_num < rdistif_num);
331 rdistif_base_addrs[proc_num] = rdistif_base;
332 rdistif_base += (1 << GICR_PCPUBASE_SHIFT);
333 } while (!(typer_val & TYPER_LAST_BIT));
334}
335
336/*******************************************************************************
337 * Helper function to configure the default attributes of SPIs.
338 ******************************************************************************/
339void gicv3_spis_configure_defaults(uintptr_t gicd_base)
340{
341 unsigned int index, num_ints;
342
343 num_ints = gicd_read_typer(gicd_base);
344 num_ints &= TYPER_IT_LINES_NO_MASK;
345 num_ints = (num_ints + 1) << 5;
346
347 /*
348 * Treat all SPIs as G1NS by default. The number of interrupts is
349 * calculated as 32 * (IT_LINES + 1). We do 32 at a time.
350 */
351 for (index = MIN_SPI_ID; index < num_ints; index += 32)
352 gicd_write_igroupr(gicd_base, index, ~0U);
353
354 /* Setup the default SPI priorities doing four at a time */
355 for (index = MIN_SPI_ID; index < num_ints; index += 4)
356 gicd_write_ipriorityr(gicd_base,
357 index,
358 GICD_IPRIORITYR_DEF_VAL);
359
360 /*
361 * Treat all SPIs as level triggered by default, write 16 at
362 * a time
363 */
364 for (index = MIN_SPI_ID; index < num_ints; index += 16)
365 gicd_write_icfgr(gicd_base, index, 0);
366}
367
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100368#if !ERROR_DEPRECATED
Achin Gupta92712a52015-09-03 14:18:02 +0100369/*******************************************************************************
370 * Helper function to configure secure G0 and G1S SPIs.
371 ******************************************************************************/
372void gicv3_secure_spis_configure(uintptr_t gicd_base,
373 unsigned int num_ints,
374 const unsigned int *sec_intr_list,
375 unsigned int int_grp)
376{
377 unsigned int index, irq_num;
Soby Mathewa0fedc42016-06-16 14:52:04 +0100378 unsigned long long gic_affinity_val;
Achin Gupta92712a52015-09-03 14:18:02 +0100379
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000380 assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
Achin Gupta92712a52015-09-03 14:18:02 +0100381 /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
382 assert(num_ints ? (uintptr_t)sec_intr_list : 1);
383
384 for (index = 0; index < num_ints; index++) {
385 irq_num = sec_intr_list[index];
386 if (irq_num >= MIN_SPI_ID) {
387
388 /* Configure this interrupt as a secure interrupt */
389 gicd_clr_igroupr(gicd_base, irq_num);
390
391 /* Configure this interrupt as G0 or a G1S interrupt */
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000392 if (int_grp == INTR_GROUP1S)
Achin Gupta92712a52015-09-03 14:18:02 +0100393 gicd_set_igrpmodr(gicd_base, irq_num);
394 else
395 gicd_clr_igrpmodr(gicd_base, irq_num);
396
397 /* Set the priority of this interrupt */
Soby Mathew421259e2016-01-15 14:20:57 +0000398 gicd_set_ipriorityr(gicd_base,
Achin Gupta92712a52015-09-03 14:18:02 +0100399 irq_num,
400 GIC_HIGHEST_SEC_PRIORITY);
401
402 /* Target SPIs to the primary CPU */
403 gic_affinity_val =
404 gicd_irouter_val_from_mpidr(read_mpidr(), 0);
405 gicd_write_irouter(gicd_base,
406 irq_num,
407 gic_affinity_val);
408
409 /* Enable this interrupt */
410 gicd_set_isenabler(gicd_base, irq_num);
411 }
412 }
413
414}
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100415#endif
Achin Gupta92712a52015-09-03 14:18:02 +0100416
417/*******************************************************************************
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100418 * Helper function to configure properties of secure SPIs
419 ******************************************************************************/
420unsigned int gicv3_secure_spis_configure_props(uintptr_t gicd_base,
421 const interrupt_prop_t *interrupt_props,
422 unsigned int interrupt_props_num)
423{
424 unsigned int i;
425 const interrupt_prop_t *current_prop;
426 unsigned long long gic_affinity_val;
427 unsigned int ctlr_enable = 0;
428
429 /* Make sure there's a valid property array */
430 assert(interrupt_props != NULL);
431 assert(interrupt_props_num > 0);
432
433 for (i = 0; i < interrupt_props_num; i++) {
434 current_prop = &interrupt_props[i];
435
436 if (current_prop->intr_num < MIN_SPI_ID)
437 continue;
438
439 /* Configure this interrupt as a secure interrupt */
440 gicd_clr_igroupr(gicd_base, current_prop->intr_num);
441
442 /* Configure this interrupt as G0 or a G1S interrupt */
443 assert((current_prop->intr_grp == INTR_GROUP0) ||
444 (current_prop->intr_grp == INTR_GROUP1S));
445 if (current_prop->intr_grp == INTR_GROUP1S) {
446 gicd_set_igrpmodr(gicd_base, current_prop->intr_num);
447 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
448 } else {
449 gicd_clr_igrpmodr(gicd_base, current_prop->intr_num);
450 ctlr_enable |= CTLR_ENABLE_G0_BIT;
451 }
452
453 /* Set interrupt configuration */
454 gicd_set_icfgr(gicd_base, current_prop->intr_num,
455 current_prop->intr_cfg);
456
457 /* Set the priority of this interrupt */
458 gicd_set_ipriorityr(gicd_base, current_prop->intr_num,
459 current_prop->intr_pri);
460
461 /* Target SPIs to the primary CPU */
462 gic_affinity_val = gicd_irouter_val_from_mpidr(read_mpidr(), 0);
463 gicd_write_irouter(gicd_base, current_prop->intr_num,
464 gic_affinity_val);
465
466 /* Enable this interrupt */
467 gicd_set_isenabler(gicd_base, current_prop->intr_num);
468 }
469
470 return ctlr_enable;
471}
472
473/*******************************************************************************
Achin Gupta92712a52015-09-03 14:18:02 +0100474 * Helper function to configure the default attributes of SPIs.
475 ******************************************************************************/
476void gicv3_ppi_sgi_configure_defaults(uintptr_t gicr_base)
477{
478 unsigned int index;
479
480 /*
481 * Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
482 * more scalable approach as it avoids clearing the enable bits in the
483 * GICD_CTLR
484 */
485 gicr_write_icenabler0(gicr_base, ~0);
486 gicr_wait_for_pending_write(gicr_base);
487
488 /* Treat all SGIs/PPIs as G1NS by default. */
489 gicr_write_igroupr0(gicr_base, ~0U);
490
491 /* Setup the default PPI/SGI priorities doing four at a time */
492 for (index = 0; index < MIN_SPI_ID; index += 4)
493 gicr_write_ipriorityr(gicr_base,
494 index,
495 GICD_IPRIORITYR_DEF_VAL);
496
497 /* Configure all PPIs as level triggered by default */
498 gicr_write_icfgr1(gicr_base, 0);
499}
500
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100501#if !ERROR_DEPRECATED
Achin Gupta92712a52015-09-03 14:18:02 +0100502/*******************************************************************************
503 * Helper function to configure secure G0 and G1S SPIs.
504 ******************************************************************************/
505void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
506 unsigned int num_ints,
507 const unsigned int *sec_intr_list,
508 unsigned int int_grp)
509{
510 unsigned int index, irq_num;
511
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000512 assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
Achin Gupta92712a52015-09-03 14:18:02 +0100513 /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
514 assert(num_ints ? (uintptr_t)sec_intr_list : 1);
515
516 for (index = 0; index < num_ints; index++) {
517 irq_num = sec_intr_list[index];
518 if (irq_num < MIN_SPI_ID) {
519
520 /* Configure this interrupt as a secure interrupt */
521 gicr_clr_igroupr0(gicr_base, irq_num);
522
523 /* Configure this interrupt as G0 or a G1S interrupt */
Soby Mathew5c5c36b2015-12-03 14:12:54 +0000524 if (int_grp == INTR_GROUP1S)
Achin Gupta92712a52015-09-03 14:18:02 +0100525 gicr_set_igrpmodr0(gicr_base, irq_num);
526 else
527 gicr_clr_igrpmodr0(gicr_base, irq_num);
528
529 /* Set the priority of this interrupt */
Soby Mathew421259e2016-01-15 14:20:57 +0000530 gicr_set_ipriorityr(gicr_base,
Achin Gupta92712a52015-09-03 14:18:02 +0100531 irq_num,
532 GIC_HIGHEST_SEC_PRIORITY);
533
534 /* Enable this interrupt */
535 gicr_set_isenabler0(gicr_base, irq_num);
536 }
537 }
538}
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100539#endif
540
541/*******************************************************************************
542 * Helper function to configure properties of secure G0 and G1S PPIs and SGIs.
543 ******************************************************************************/
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000544unsigned int gicv3_secure_ppi_sgi_configure_props(uintptr_t gicr_base,
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100545 const interrupt_prop_t *interrupt_props,
546 unsigned int interrupt_props_num)
547{
548 unsigned int i;
549 const interrupt_prop_t *current_prop;
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000550 unsigned int ctlr_enable = 0;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100551
552 /* Make sure there's a valid property array */
553 assert(interrupt_props != NULL);
554 assert(interrupt_props_num > 0);
555
556 for (i = 0; i < interrupt_props_num; i++) {
557 current_prop = &interrupt_props[i];
558
559 if (current_prop->intr_num >= MIN_SPI_ID)
560 continue;
561
562 /* Configure this interrupt as a secure interrupt */
563 gicr_clr_igroupr0(gicr_base, current_prop->intr_num);
564
565 /* Configure this interrupt as G0 or a G1S interrupt */
566 assert((current_prop->intr_grp == INTR_GROUP0) ||
567 (current_prop->intr_grp == INTR_GROUP1S));
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000568 if (current_prop->intr_grp == INTR_GROUP1S) {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100569 gicr_set_igrpmodr0(gicr_base, current_prop->intr_num);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000570 ctlr_enable |= CTLR_ENABLE_G1S_BIT;
571 } else {
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100572 gicr_clr_igrpmodr0(gicr_base, current_prop->intr_num);
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000573 ctlr_enable |= CTLR_ENABLE_G0_BIT;
574 }
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100575
576 /* Set the priority of this interrupt */
577 gicr_set_ipriorityr(gicr_base, current_prop->intr_num,
578 current_prop->intr_pri);
579
580 /*
581 * Set interrupt configuration for PPIs. Configuration for SGIs
582 * are ignored.
583 */
584 if ((current_prop->intr_num >= MIN_PPI_ID) &&
585 (current_prop->intr_num < MIN_SPI_ID)) {
586 gicr_set_icfgr1(gicr_base, current_prop->intr_num,
587 current_prop->intr_cfg);
588 }
589
590 /* Enable this interrupt */
591 gicr_set_isenabler0(gicr_base, current_prop->intr_num);
592 }
Jeenu Viswambharan88d8f452017-11-07 08:38:23 +0000593
594 return ctlr_enable;
Jeenu Viswambharanaeb267c2017-09-22 08:32:09 +0100595}