Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 7 | #include <assert.h> |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 8 | #include <cortex_a57.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <arch_helpers.h> |
| 10 | #include <common/debug.h> |
| 11 | #include <drivers/delay_timer.h> |
| 12 | #include <lib/mmio.h> |
| 13 | #include <lib/psci/psci.h> |
| 14 | #include <plat/common/platform.h> |
| 15 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 16 | #include <bpmp.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 17 | #include <flowctrl.h> |
Ambroise Vincent | ffbf32a | 2019-03-28 09:01:18 +0000 | [diff] [blame] | 18 | #include <lib/utils.h> |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 19 | #include <memctrl.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 20 | #include <pmc.h> |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 21 | #include <platform_def.h> |
| 22 | #include <security_engine.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 23 | #include <tegra_def.h> |
| 24 | #include <tegra_private.h> |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 25 | #include <tegra_platform.h> |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 26 | |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 27 | /* |
| 28 | * Register used to clear CPU reset signals. Each CPU has two reset |
| 29 | * signals: CPU reset (3:0) and Core reset (19:16). |
| 30 | */ |
| 31 | #define CPU_CMPLX_RESET_CLR 0x454 |
| 32 | #define CPU_CORE_RESET_MASK 0x10001 |
| 33 | |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 34 | /* Clock and Reset controller registers for system clock's settings */ |
| 35 | #define SCLK_RATE 0x30 |
| 36 | #define SCLK_BURST_POLICY 0x28 |
| 37 | #define SCLK_BURST_POLICY_DEFAULT 0x10000000 |
| 38 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 39 | static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 40 | static bool tegra_bpmp_available = true; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 41 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 42 | int32_t tegra_soc_validate_power_state(unsigned int power_state, |
| 43 | psci_power_state_t *req_state) |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 44 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 45 | int state_id = psci_get_pstate_id(power_state); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 46 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 47 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 48 | /* Sanity check the requested state id */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 49 | switch (state_id) { |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 50 | case PSTATE_ID_CORE_POWERDN: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 51 | /* |
| 52 | * Core powerdown request only for afflvl 0 |
| 53 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 54 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; |
| 55 | |
| 56 | break; |
| 57 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 58 | case PSTATE_ID_CLUSTER_IDLE: |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 59 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 60 | /* |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 61 | * Cluster idle request for afflvl 0 |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 62 | */ |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 63 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 64 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 65 | break; |
| 66 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 67 | case PSTATE_ID_SOC_POWERDN: |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 68 | |
| 69 | /* |
| 70 | * sc7entry-fw must be present in the system when the bpmp |
| 71 | * firmware is not present, for a successful System Suspend |
| 72 | * entry. |
| 73 | */ |
| 74 | if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base) |
| 75 | return PSCI_E_NOT_SUPPORTED; |
| 76 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 77 | /* |
| 78 | * System powerdown request only for afflvl 2 |
| 79 | */ |
Varun Wadekar | 66231d1 | 2017-06-07 09:57:42 -0700 | [diff] [blame] | 80 | for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 81 | req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE; |
| 82 | |
| 83 | req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = |
| 84 | PLAT_SYS_SUSPEND_STATE_ID; |
| 85 | |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 86 | break; |
| 87 | |
| 88 | default: |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 89 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
| 90 | return PSCI_E_INVALID_PARAMS; |
Varun Wadekar | 254441d | 2015-07-23 10:07:54 +0530 | [diff] [blame] | 91 | } |
| 92 | |
| 93 | return PSCI_E_SUCCESS; |
| 94 | } |
| 95 | |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 96 | /******************************************************************************* |
| 97 | * Platform handler to calculate the proper target power level at the |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 98 | * specified affinity level. |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 99 | ******************************************************************************/ |
| 100 | plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, |
| 101 | const plat_local_state_t *states, |
| 102 | unsigned int ncpu) |
| 103 | { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 104 | plat_local_state_t target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 105 | int cpu = plat_my_core_pos(); |
| 106 | int core_pos = read_mpidr() & MPIDR_CPU_MASK; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 107 | uint32_t bpmp_reply, data[3], val; |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 108 | int ret; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 109 | |
| 110 | /* get the power state at this level */ |
| 111 | if (lvl == MPIDR_AFFLVL1) |
| 112 | target = *(states + core_pos); |
| 113 | if (lvl == MPIDR_AFFLVL2) |
| 114 | target = *(states + cpu); |
| 115 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 116 | if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_IDLE)) { |
| 117 | |
| 118 | /* initialize the bpmp interface */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 119 | ret = tegra_bpmp_init(); |
| 120 | if (ret != 0U) { |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 121 | |
Varun Wadekar | 22ecc05 | 2018-04-19 17:50:31 -0700 | [diff] [blame] | 122 | /* |
| 123 | * flag to indicate that BPMP firmware is not |
| 124 | * available and the CPU has to handle entry/exit |
| 125 | * for all power states |
| 126 | */ |
| 127 | tegra_bpmp_available = false; |
| 128 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 129 | /* Cluster idle not allowed */ |
| 130 | target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 131 | |
| 132 | /******************************************* |
| 133 | * BPMP is not present, so handle CC6 entry |
| 134 | * from the CPU |
| 135 | ******************************************/ |
| 136 | |
| 137 | /* check if cluster idle state has been enabled */ |
| 138 | val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL); |
| 139 | if (val == ENABLE_CLOSED_LOOP) { |
| 140 | /* |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 141 | * Acquire the cluster idle lock to stop |
| 142 | * other CPUs from powering up. |
| 143 | */ |
| 144 | tegra_fc_ccplex_pgexit_lock(); |
| 145 | |
| 146 | /* Cluster idle only from the last standing CPU */ |
| 147 | if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) { |
| 148 | /* Cluster idle allowed */ |
| 149 | target = PSTATE_ID_CLUSTER_IDLE; |
| 150 | } else { |
| 151 | /* release cluster idle lock */ |
| 152 | tegra_fc_ccplex_pgexit_unlock(); |
| 153 | } |
| 154 | } |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 155 | } else { |
| 156 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 157 | /* Cluster power-down */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 158 | data[0] = (uint32_t)cpu; |
| 159 | data[1] = TEGRA_PM_CC6; |
| 160 | data[2] = TEGRA_PM_SC1; |
| 161 | ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, |
| 162 | (void *)&data, (int)sizeof(data), |
| 163 | (void *)&bpmp_reply, |
| 164 | (int)sizeof(bpmp_reply)); |
| 165 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 166 | /* check if cluster power down is allowed */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 167 | if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) { |
| 168 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 169 | /* Cluster power down not allowed */ |
Varun Wadekar | a9a3a10 | 2017-08-23 10:19:25 -0700 | [diff] [blame] | 170 | target = PSCI_LOCAL_STATE_RUN; |
| 171 | } |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 172 | } |
| 173 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 174 | } else if (((lvl == MPIDR_AFFLVL2) || (lvl == MPIDR_AFFLVL1)) && |
| 175 | (target == PSTATE_ID_SOC_POWERDN)) { |
| 176 | |
| 177 | /* System Suspend */ |
| 178 | target = PSTATE_ID_SOC_POWERDN; |
| 179 | |
| 180 | } else { |
| 181 | ; /* do nothing */ |
| 182 | } |
| 183 | |
| 184 | return target; |
Varun Wadekar | b91b5fc | 2017-04-18 11:22:01 -0700 | [diff] [blame] | 185 | } |
| 186 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 187 | int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 188 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 189 | u_register_t mpidr = read_mpidr(); |
| 190 | const plat_local_state_t *pwr_domain_state = |
| 191 | target_state->pwr_domain_state; |
| 192 | unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; |
| 193 | unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; |
| 194 | unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 195 | uint32_t cfg; |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 196 | int ret = PSCI_E_SUCCESS; |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 197 | uint32_t val; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 198 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 199 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 200 | |
Harvey Hsieh | 20e9fef | 2016-12-28 21:53:18 +0800 | [diff] [blame] | 201 | assert((stateid_afflvl0 == PLAT_MAX_OFF_STATE) || |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 202 | (stateid_afflvl0 == PSTATE_ID_SOC_POWERDN)); |
Harvey Hsieh | 20e9fef | 2016-12-28 21:53:18 +0800 | [diff] [blame] | 203 | assert((stateid_afflvl1 == PLAT_MAX_OFF_STATE) || |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 204 | (stateid_afflvl1 == PSTATE_ID_SOC_POWERDN)); |
| 205 | |
| 206 | if (tegra_chipid_is_t210_b01()) { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 207 | |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 208 | /* Suspend se/se2 and pka1 */ |
| 209 | if (tegra_se_suspend() != 0) { |
| 210 | ret = PSCI_E_INTERN_FAIL; |
| 211 | } |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 212 | } |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 213 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 214 | } else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_IDLE) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 215 | |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 216 | assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 217 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 218 | if (!tegra_bpmp_available) { |
| 219 | |
Varun Wadekar | 22ecc05 | 2018-04-19 17:50:31 -0700 | [diff] [blame] | 220 | /* |
| 221 | * When disabled, DFLL loses its state. Enable |
| 222 | * open loop state for the DFLL as we dont want |
| 223 | * garbage values being written to the pmic |
| 224 | * when we enter cluster idle state. |
| 225 | */ |
| 226 | mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL, |
| 227 | ENABLE_OPEN_LOOP); |
| 228 | |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 229 | /* Find if the platform uses OVR2/MAX77621 PMIC */ |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 230 | cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); |
| 231 | if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 232 | /* OVR2 */ |
| 233 | |
| 234 | /* PWM tristate */ |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 235 | val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); |
| 236 | val |= PINMUX_PWM_TRISTATE; |
| 237 | mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 238 | |
| 239 | /* |
| 240 | * SCRATCH201[1] is being used to identify CPU |
| 241 | * PMIC in warmboot code. |
| 242 | * 0 : OVR2 |
| 243 | * 1 : MAX77621 |
| 244 | */ |
| 245 | tegra_pmc_write_32(PMC_SCRATCH201, 0x0); |
| 246 | } else { |
| 247 | /* MAX77621 */ |
| 248 | tegra_pmc_write_32(PMC_SCRATCH201, 0x2); |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 249 | } |
| 250 | } |
| 251 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 252 | /* Prepare for cluster idle */ |
| 253 | tegra_fc_cluster_idle(mpidr); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 254 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 255 | } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { |
| 256 | |
| 257 | /* Prepare for cpu powerdn */ |
| 258 | tegra_fc_cpu_powerdn(mpidr); |
| 259 | |
| 260 | } else { |
Varun Wadekar | a6a357f | 2017-05-05 09:20:59 -0700 | [diff] [blame] | 261 | ERROR("%s: Unknown state id (%d, %d, %d)\n", __func__, |
| 262 | stateid_afflvl2, stateid_afflvl1, stateid_afflvl0); |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 263 | ret = PSCI_E_NOT_SUPPORTED; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 264 | } |
| 265 | |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 266 | return ret; |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 267 | } |
| 268 | |
Varun Wadekar | dae2796 | 2018-03-05 10:19:37 -0800 | [diff] [blame] | 269 | static void tegra_reset_all_dma_masters(void) |
| 270 | { |
| 271 | uint32_t val, mask; |
| 272 | |
| 273 | /* |
| 274 | * Reset all possible DMA masters in the system. |
| 275 | */ |
| 276 | val = GPU_RESET_BIT; |
| 277 | mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val); |
| 278 | |
| 279 | val = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | |
| 280 | NVJPG_RESET_BIT | NVDEC_RESET_BIT; |
| 281 | mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y, val); |
| 282 | |
| 283 | val = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | |
| 284 | VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT | |
| 285 | SDMMC2_RESET_BIT; |
| 286 | mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L, val); |
| 287 | |
| 288 | val = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; |
| 289 | mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H, val); |
| 290 | |
| 291 | val = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | |
| 292 | PCIE_RESET_BIT | SDMMC3_RESET_BIT; |
| 293 | mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U, val); |
| 294 | |
| 295 | val = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT; |
| 296 | mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V, val); |
| 297 | |
| 298 | /* |
| 299 | * If any of the DMA masters are still alive, assume |
| 300 | * that the system has been compromised and reboot. |
| 301 | */ |
| 302 | val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET); |
| 303 | mask = GPU_RESET_BIT; |
| 304 | if ((val & mask) != mask) |
| 305 | tegra_pmc_system_reset(); |
| 306 | |
| 307 | mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | |
| 308 | NVJPG_RESET_BIT | NVDEC_RESET_BIT; |
| 309 | val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y); |
| 310 | if ((val & mask) != mask) |
| 311 | tegra_pmc_system_reset(); |
| 312 | |
| 313 | mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | |
| 314 | VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT | |
| 315 | SDMMC2_RESET_BIT; |
| 316 | val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L); |
| 317 | if ((val & mask) != mask) |
| 318 | tegra_pmc_system_reset(); |
| 319 | |
| 320 | mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; |
| 321 | val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H); |
| 322 | if ((val & mask) != mask) |
| 323 | tegra_pmc_system_reset(); |
| 324 | |
| 325 | mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | |
| 326 | PCIE_RESET_BIT | SDMMC3_RESET_BIT; |
| 327 | val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U); |
| 328 | if ((val & mask) != mask) |
| 329 | tegra_pmc_system_reset(); |
| 330 | |
| 331 | val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V); |
| 332 | mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT; |
| 333 | if ((val & mask) != mask) |
| 334 | tegra_pmc_system_reset(); |
| 335 | } |
| 336 | |
Harvey Hsieh | a16d4ea | 2017-06-15 16:28:43 -0700 | [diff] [blame] | 337 | int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
| 338 | { |
| 339 | u_register_t mpidr = read_mpidr(); |
| 340 | const plat_local_state_t *pwr_domain_state = |
| 341 | target_state->pwr_domain_state; |
| 342 | unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 343 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
| 344 | uint32_t val; |
Harvey Hsieh | a16d4ea | 2017-06-15 16:28:43 -0700 | [diff] [blame] | 345 | |
| 346 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 347 | |
| 348 | if (tegra_chipid_is_t210_b01()) { |
| 349 | /* Save tzram contents */ |
| 350 | tegra_se_save_tzram(); |
| 351 | } |
| 352 | |
Varun Wadekar | a6daf1c | 2018-04-04 11:14:05 -0700 | [diff] [blame] | 353 | /* de-init the interface */ |
| 354 | tegra_bpmp_suspend(); |
| 355 | |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 356 | /* |
| 357 | * The CPU needs to load the System suspend entry firmware |
| 358 | * if nothing is running on the BPMP. |
| 359 | */ |
| 360 | if (!tegra_bpmp_available) { |
| 361 | |
| 362 | /* |
| 363 | * BPMP firmware is not running on the co-processor, so |
| 364 | * we need to explicitly load the firmware to enable |
| 365 | * entry/exit to/from System Suspend and set the BPMP |
| 366 | * on its way. |
| 367 | */ |
| 368 | |
| 369 | /* Power off BPMP before we proceed */ |
| 370 | tegra_fc_bpmp_off(); |
| 371 | |
Varun Wadekar | dae2796 | 2018-03-05 10:19:37 -0800 | [diff] [blame] | 372 | /* bond out IRAM banks B, C and D */ |
| 373 | mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_U, |
| 374 | IRAM_B_LOCK_BIT | IRAM_C_LOCK_BIT | |
| 375 | IRAM_D_LOCK_BIT); |
| 376 | |
| 377 | /* bond out APB/AHB DMAs */ |
| 378 | mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_H, |
| 379 | APB_DMA_LOCK_BIT | AHB_DMA_LOCK_BIT); |
| 380 | |
| 381 | /* Power off BPMP before we proceed */ |
| 382 | tegra_fc_bpmp_off(); |
| 383 | |
| 384 | /* |
| 385 | * Reset all the hardware blocks that can act as DMA |
| 386 | * masters on the bus. |
| 387 | */ |
| 388 | tegra_reset_all_dma_masters(); |
| 389 | |
| 390 | /* clean up IRAM of any cruft */ |
| 391 | zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE, |
| 392 | TEGRA_IRAM_A_SIZE); |
| 393 | |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 394 | /* Copy the firmware to BPMP's internal RAM */ |
| 395 | (void)memcpy((void *)(uintptr_t)TEGRA_IRAM_BASE, |
Varun Wadekar | 8c6517d | 2018-03-19 15:19:28 -0700 | [diff] [blame] | 396 | (const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES), |
| 397 | plat_params->sc7entry_fw_size - SC7ENTRY_FW_HEADER_SIZE_BYTES); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 398 | |
| 399 | /* Power on the BPMP and execute from IRAM base */ |
| 400 | tegra_fc_bpmp_on(TEGRA_IRAM_BASE); |
| 401 | |
| 402 | /* Wait until BPMP powers up */ |
| 403 | do { |
| 404 | val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET); |
| 405 | } while (val != SIGN_OF_LIFE); |
| 406 | } |
| 407 | |
Harvey Hsieh | a16d4ea | 2017-06-15 16:28:43 -0700 | [diff] [blame] | 408 | /* enter system suspend */ |
| 409 | tegra_fc_soc_powerdn(mpidr); |
| 410 | } |
| 411 | |
| 412 | return PSCI_E_SUCCESS; |
| 413 | } |
| 414 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 415 | int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 416 | { |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 417 | const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 418 | uint32_t cfg; |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 419 | uint32_t val, entrypoint = 0; |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 420 | uint64_t offset; |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 421 | |
Sam Payne | 71ce6ed | 2017-05-08 12:42:49 -0700 | [diff] [blame] | 422 | /* platform parameter passed by the previous bootloader */ |
| 423 | if (plat_params->l2_ecc_parity_prot_dis != 1) { |
| 424 | /* Enable ECC Parity Protection for Cortex-A57 CPUs */ |
| 425 | val = read_l2ctlr_el1(); |
| 426 | val |= (uint64_t)CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT; |
| 427 | write_l2ctlr_el1(val); |
| 428 | } |
| 429 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 430 | /* |
| 431 | * Check if we are exiting from SOC_POWERDN. |
| 432 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 433 | if (target_state->pwr_domain_state[PLAT_MAX_PWR_LVL] == |
| 434 | PLAT_SYS_SUSPEND_STATE_ID) { |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 435 | |
| 436 | /* |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 437 | * Security engine resume |
| 438 | */ |
| 439 | if (tegra_chipid_is_t210_b01()) { |
| 440 | tegra_se_resume(); |
| 441 | } |
| 442 | |
| 443 | /* |
Varun Wadekar | 6eec6d6 | 2016-03-03 13:28:10 -0800 | [diff] [blame] | 444 | * Lock scratch registers which hold the CPU vectors |
| 445 | */ |
| 446 | tegra_pmc_lock_cpu_vectors(); |
| 447 | |
| 448 | /* |
Varun Wadekar | bc78744 | 2015-07-27 13:00:50 +0530 | [diff] [blame] | 449 | * Enable WRAP to INCR burst type conversions for |
| 450 | * incoming requests on the AXI slave ports. |
| 451 | */ |
| 452 | val = mmio_read_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG); |
| 453 | val &= ~ENABLE_UNSUP_TX_ERRORS; |
| 454 | val |= ENABLE_WRAP_TO_INCR_BURSTS; |
| 455 | mmio_write_32(TEGRA_MSELECT_BASE + MSELECT_CONFIG, val); |
| 456 | |
| 457 | /* |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 458 | * Restore Boot and Power Management Processor (BPMP) reset |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 459 | * address and reset it, if it is supported by the platform. |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 460 | */ |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 461 | if (!tegra_bpmp_available) { |
| 462 | tegra_fc_bpmp_off(); |
| 463 | } else { |
| 464 | entrypoint = tegra_pmc_read_32(PMC_SCRATCH39); |
| 465 | tegra_fc_bpmp_on(entrypoint); |
Varun Wadekar | a6daf1c | 2018-04-04 11:14:05 -0700 | [diff] [blame] | 466 | |
| 467 | /* initialise the interface */ |
| 468 | tegra_bpmp_resume(); |
Varun Wadekar | f07d6de | 2018-02-27 14:33:57 -0800 | [diff] [blame] | 469 | } |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 470 | |
| 471 | /* sc7entry-fw is part of TZDRAM area */ |
| 472 | if (plat_params->sc7entry_fw_base != 0U) { |
| 473 | offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base; |
| 474 | tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base, |
| 475 | plat_params->tzdram_size + offset); |
Varun Wadekar | a8c61ac | 2018-03-12 15:11:55 -0700 | [diff] [blame] | 476 | |
| 477 | /* restrict PMC access to secure world */ |
| 478 | val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE); |
| 479 | val |= PMC_SECURITY_EN_BIT; |
| 480 | mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val); |
Varun Wadekar | 6e29d4d | 2018-03-07 11:13:58 -0800 | [diff] [blame] | 481 | } |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 482 | } |
| 483 | |
| 484 | /* |
| 485 | * Check if we are exiting cluster idle state |
| 486 | */ |
| 487 | if (target_state->pwr_domain_state[MPIDR_AFFLVL1] == |
| 488 | PSTATE_ID_CLUSTER_IDLE) { |
| 489 | |
| 490 | if (!tegra_bpmp_available) { |
| 491 | |
| 492 | /* PWM un-tristate */ |
| 493 | cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG); |
| 494 | if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) { |
| 495 | val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); |
| 496 | val &= ~PINMUX_PWM_TRISTATE; |
| 497 | mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val); |
Varun Wadekar | 22ecc05 | 2018-04-19 17:50:31 -0700 | [diff] [blame] | 498 | |
| 499 | /* make sure the setting took effect */ |
| 500 | val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM); |
| 501 | assert((val & PINMUX_PWM_TRISTATE) == 0U); |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 502 | } |
| 503 | |
Varun Wadekar | 22ecc05 | 2018-04-19 17:50:31 -0700 | [diff] [blame] | 504 | /* |
| 505 | * Restore operation mode for the DFLL ring |
| 506 | * oscillator |
| 507 | */ |
| 508 | mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL, |
| 509 | ENABLE_CLOSED_LOOP); |
| 510 | |
Varun Wadekar | ba31328 | 2018-02-13 20:31:12 -0800 | [diff] [blame] | 511 | /* release cluster idle lock */ |
| 512 | tegra_fc_ccplex_pgexit_unlock(); |
| 513 | } |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 514 | } |
| 515 | |
| 516 | /* |
| 517 | * T210 has a dedicated ARMv7 boot and power mgmt processor, BPMP. It's |
| 518 | * used for power management and boot purposes. Inform the BPMP that |
| 519 | * we have completed the cluster power up. |
| 520 | */ |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 521 | tegra_fc_lock_active_cluster(); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 522 | |
kalyani chidambaram | b3873aa | 2018-04-09 14:40:02 -0700 | [diff] [blame] | 523 | /* |
| 524 | * Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw |
| 525 | */ |
| 526 | if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U)) |
| 527 | tegra_pmc_resume(); |
| 528 | |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 529 | return PSCI_E_SUCCESS; |
| 530 | } |
| 531 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 532 | int tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 533 | { |
| 534 | int cpu = mpidr & MPIDR_CPU_MASK; |
Varun Wadekar | 071b787 | 2015-07-08 17:42:02 +0530 | [diff] [blame] | 535 | uint32_t mask = CPU_CORE_RESET_MASK << cpu; |
| 536 | |
| 537 | /* Deassert CPU reset signals */ |
| 538 | mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 539 | |
| 540 | /* Turn on CPU using flow controller or PMC */ |
| 541 | if (cpu_powergate_mask[cpu] == 0) { |
| 542 | tegra_pmc_cpu_on(cpu); |
| 543 | cpu_powergate_mask[cpu] = 1; |
| 544 | } else { |
| 545 | tegra_fc_cpu_on(cpu); |
| 546 | } |
| 547 | |
| 548 | return PSCI_E_SUCCESS; |
| 549 | } |
| 550 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 551 | int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 552 | { |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 553 | tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK); |
Varun Wadekar | b316e24 | 2015-05-19 16:48:04 +0530 | [diff] [blame] | 554 | return PSCI_E_SUCCESS; |
| 555 | } |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 556 | |
| 557 | int tegra_soc_prepare_system_reset(void) |
| 558 | { |
| 559 | /* |
| 560 | * Set System Clock (SCLK) to POR default so that the clock source |
| 561 | * for the PMC APB clock would not be changed due to system reset. |
| 562 | */ |
| 563 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_BURST_POLICY, |
Marvin Hsu | 21eea97 | 2017-04-11 11:00:48 +0800 | [diff] [blame] | 564 | SCLK_BURST_POLICY_DEFAULT); |
Varun Wadekar | 8b82fae | 2015-11-09 17:39:28 -0800 | [diff] [blame] | 565 | mmio_write_32((uintptr_t)TEGRA_CAR_RESET_BASE + SCLK_RATE, 0); |
| 566 | |
| 567 | /* Wait 1 ms to make sure clock source/device logic is stabilized. */ |
| 568 | mdelay(1); |
| 569 | |
| 570 | return PSCI_E_SUCCESS; |
| 571 | } |