Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 8 | #include <assert.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 9 | #include <stdbool.h> |
| 10 | #include <string.h> |
| 11 | |
| 12 | #include <arch_helpers.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 13 | #include <common/bl_common.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 14 | #include <common/debug.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 15 | #include <context.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 16 | #include <denver.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 17 | #include <lib/el3_runtime/context_mgmt.h> |
| 18 | #include <lib/psci/psci.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 19 | #include <mce.h> |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 20 | #include <mce_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 21 | #include <plat/common/platform.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 22 | #include <se.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 23 | #include <smmu.h> |
Tejal Kudav | 153ba22 | 2017-02-14 18:02:04 -0800 | [diff] [blame] | 24 | #include <t194_nvg.h> |
Varun Wadekar | e0c222f | 2017-11-10 13:23:34 -0800 | [diff] [blame] | 25 | #include <tegra194_private.h> |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 26 | #include <tegra_platform.h> |
| 27 | #include <tegra_private.h> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 28 | |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 29 | extern void tegra194_cpu_reset_handler(void); |
| 30 | extern uint32_t __tegra194_cpu_reset_handler_data, |
| 31 | __tegra194_cpu_reset_handler_end; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 32 | |
| 33 | /* TZDRAM offset for saving SMMU context */ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 34 | #define TEGRA194_SMMU_CTX_OFFSET 16U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 35 | |
| 36 | /* state id mask */ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 37 | #define TEGRA194_STATE_ID_MASK 0xFU |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 38 | /* constants to get power state's wake time */ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 39 | #define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U |
| 40 | #define TEGRA194_WAKE_TIME_SHIFT 4U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 41 | /* default core wake mask for CPU_SUSPEND */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 42 | #define TEGRA194_CORE_WAKE_MASK 0x180cU |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 43 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 44 | static struct t19x_psci_percpu_data { |
| 45 | uint32_t wake_time; |
| 46 | } __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT]; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 47 | |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 48 | /* |
| 49 | * tegra_fake_system_suspend acts as a boolean var controlling whether |
| 50 | * we are going to take fake system suspend code or normal system suspend code |
| 51 | * path. This variable is set inside the sip call handlers, when the kernel |
| 52 | * requests an SIP call to set the suspend debug flags. |
| 53 | */ |
| 54 | bool tegra_fake_system_suspend; |
| 55 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 56 | int32_t tegra_soc_validate_power_state(uint32_t power_state, |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 57 | psci_power_state_t *req_state) |
| 58 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 59 | uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) & |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 60 | TEGRA194_STATE_ID_MASK; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 61 | uint32_t cpu = plat_my_core_pos(); |
| 62 | int32_t ret = PSCI_E_SUCCESS; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 63 | |
| 64 | /* save the core wake time (in TSC ticks)*/ |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 65 | t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK) |
| 66 | << TEGRA194_WAKE_TIME_SHIFT; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 67 | |
| 68 | /* |
Varun Wadekar | 56c6459 | 2019-12-03 08:50:57 -0800 | [diff] [blame] | 69 | * Clean t19x_percpu_data[cpu] to DRAM. This needs to be done to ensure |
| 70 | * that the correct value is read in tegra_soc_pwr_domain_suspend(), |
| 71 | * which is called with caches disabled. It is possible to read a stale |
| 72 | * value from DRAM in that function, because the L2 cache is not flushed |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 73 | * unless the cluster is entering CC6/CC7. |
| 74 | */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 75 | clean_dcache_range((uint64_t)&t19x_percpu_data[cpu], |
| 76 | sizeof(t19x_percpu_data[cpu])); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 77 | |
| 78 | /* Sanity check the requested state id */ |
| 79 | switch (state_id) { |
| 80 | case PSTATE_ID_CORE_IDLE: |
| 81 | case PSTATE_ID_CORE_POWERDN: |
| 82 | |
| 83 | /* Core powerdown request */ |
| 84 | req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; |
| 85 | req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id; |
| 86 | |
| 87 | break; |
| 88 | |
| 89 | default: |
| 90 | ERROR("%s: unsupported state id (%d)\n", __func__, state_id); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 91 | ret = PSCI_E_INVALID_PARAMS; |
| 92 | break; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 93 | } |
| 94 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 95 | return ret; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 96 | } |
| 97 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 98 | int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 99 | { |
| 100 | const plat_local_state_t *pwr_domain_state; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 101 | uint8_t stateid_afflvl0, stateid_afflvl2; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 102 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 103 | uint64_t smmu_ctx_base; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 104 | uint32_t val; |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 105 | mce_cstate_info_t sc7_cstate_info = { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 106 | .cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6, |
| 107 | .system = (uint32_t)TEGRA_NVG_SYSTEM_SC7, |
| 108 | .system_state_force = 1U, |
| 109 | .update_wake_mask = 1U, |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 110 | }; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 111 | uint32_t cpu = plat_my_core_pos(); |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 112 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 113 | |
| 114 | /* get the state ID */ |
| 115 | pwr_domain_state = target_state->pwr_domain_state; |
| 116 | stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 117 | TEGRA194_STATE_ID_MASK; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 118 | stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 119 | TEGRA194_STATE_ID_MASK; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 120 | |
| 121 | if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) || |
| 122 | (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) { |
| 123 | |
| 124 | /* Enter CPU idle/powerdown */ |
Krishna Sitaraman | c64afeb | 2017-01-23 16:15:44 -0800 | [diff] [blame] | 125 | val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ? |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 126 | (uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7; |
| 127 | ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val, |
Varun Wadekar | 56c6459 | 2019-12-03 08:50:57 -0800 | [diff] [blame] | 128 | t19x_percpu_data[cpu].wake_time, 0); |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 129 | assert(ret == 0); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 130 | |
| 131 | } else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 132 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 133 | /* save 'Secure Boot' Processor Feature Config Register */ |
| 134 | val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG); |
Steven Kao | 4607f17 | 2017-10-23 18:35:14 +0800 | [diff] [blame] | 135 | mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 136 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 137 | /* save SMMU context */ |
| 138 | smmu_ctx_base = params_from_bl2->tzdram_base + |
Varun Wadekar | e0c222f | 2017-11-10 13:23:34 -0800 | [diff] [blame] | 139 | tegra194_get_smmu_ctx_offset(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 140 | tegra_smmu_save_context((uintptr_t)smmu_ctx_base); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 141 | |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 142 | /* |
| 143 | * Suspend SE, RNG1 and PKA1 only on silcon and fpga, |
| 144 | * since VDK does not support atomic se ctx save |
| 145 | */ |
| 146 | if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) { |
| 147 | ret = tegra_se_suspend(); |
| 148 | assert(ret == 0); |
| 149 | } |
| 150 | |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 151 | if (!tegra_fake_system_suspend) { |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 152 | |
| 153 | /* Prepare for system suspend */ |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 154 | mce_update_cstate_info(&sc7_cstate_info); |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 155 | |
| 156 | do { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 157 | val = (uint32_t)mce_command_handler( |
| 158 | (uint32_t)MCE_CMD_IS_SC7_ALLOWED, |
| 159 | (uint32_t)TEGRA_NVG_CORE_C7, |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 160 | MCE_CORE_SLEEP_TIME_INFINITE, |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 161 | 0U); |
| 162 | } while (val == 0U); |
Tejal Kudav | 153ba22 | 2017-02-14 18:02:04 -0800 | [diff] [blame] | 163 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 164 | /* Instruct the MCE to enter system suspend state */ |
| 165 | ret = mce_command_handler( |
| 166 | (uint64_t)MCE_CMD_ENTER_CSTATE, |
| 167 | (uint64_t)TEGRA_NVG_CORE_C7, |
| 168 | MCE_CORE_SLEEP_TIME_INFINITE, |
| 169 | 0U); |
| 170 | assert(ret == 0); |
Varun Wadekar | da865de | 2017-11-10 13:27:29 -0800 | [diff] [blame] | 171 | |
| 172 | /* set system suspend state for house-keeping */ |
| 173 | tegra194_set_system_suspend_entry(); |
Vignesh Radhakrishnan | 0e2502f | 2017-04-10 15:07:39 -0700 | [diff] [blame] | 174 | } |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 175 | } else { |
| 176 | ; /* do nothing */ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | return PSCI_E_SUCCESS; |
| 180 | } |
| 181 | |
| 182 | /******************************************************************************* |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 183 | * Helper function to check if this is the last ON CPU in the cluster |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 184 | ******************************************************************************/ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 185 | static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states, |
| 186 | uint32_t ncpu) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 187 | { |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 188 | plat_local_state_t target; |
| 189 | bool last_on_cpu = true; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 190 | uint32_t num_cpus = ncpu, pos = 0; |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 191 | |
| 192 | do { |
| 193 | target = states[pos]; |
| 194 | if (target != PLAT_MAX_OFF_STATE) { |
| 195 | last_on_cpu = false; |
| 196 | } |
| 197 | --num_cpus; |
| 198 | pos++; |
| 199 | } while (num_cpus != 0U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 200 | |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 201 | return last_on_cpu; |
| 202 | } |
| 203 | |
| 204 | /******************************************************************************* |
| 205 | * Helper function to get target power state for the cluster |
| 206 | ******************************************************************************/ |
| 207 | static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states, |
| 208 | uint32_t ncpu) |
| 209 | { |
| 210 | uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK; |
| 211 | plat_local_state_t target = states[core_pos]; |
| 212 | mce_cstate_info_t cstate_info = { 0 }; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 213 | |
| 214 | /* CPU suspend */ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 215 | if (target == PSTATE_ID_CORE_POWERDN) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 216 | |
| 217 | /* Program default wake mask */ |
Krishna Sitaraman | c64afeb | 2017-01-23 16:15:44 -0800 | [diff] [blame] | 218 | cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK; |
| 219 | cstate_info.update_wake_mask = 1; |
| 220 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 221 | } |
| 222 | |
| 223 | /* CPU off */ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 224 | if (target == PLAT_MAX_OFF_STATE) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 225 | |
| 226 | /* Enable cluster powerdn from last CPU in the cluster */ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 227 | if (tegra_last_on_cpu_in_cluster(states, ncpu)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 228 | |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 229 | /* Enable CC6 state and turn off wake mask */ |
| 230 | cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6; |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 231 | cstate_info.update_wake_mask = 1U; |
| 232 | mce_update_cstate_info(&cstate_info); |
| 233 | |
| 234 | } else { |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 235 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 236 | /* Turn off wake_mask */ |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 237 | cstate_info.update_wake_mask = 1U; |
| 238 | mce_update_cstate_info(&cstate_info); |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 239 | target = PSCI_LOCAL_STATE_RUN; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 240 | } |
| 241 | } |
| 242 | |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 243 | return target; |
| 244 | } |
| 245 | |
| 246 | /******************************************************************************* |
| 247 | * Platform handler to calculate the proper target power level at the |
| 248 | * specified affinity level |
| 249 | ******************************************************************************/ |
| 250 | plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, |
| 251 | const plat_local_state_t *states, |
| 252 | uint32_t ncpu) |
| 253 | { |
| 254 | plat_local_state_t target = PSCI_LOCAL_STATE_RUN; |
| 255 | uint32_t cpu = plat_my_core_pos(); |
| 256 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 257 | /* System Suspend */ |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 258 | if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) { |
| 259 | target = PSTATE_ID_SOC_POWERDN; |
| 260 | } |
| 261 | |
| 262 | /* CPU off, CPU suspend */ |
| 263 | if (lvl == (uint32_t)MPIDR_AFFLVL1) { |
| 264 | target = tegra_get_afflvl1_pwr_state(states, ncpu); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 265 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 266 | |
Varun Wadekar | 0723bb6 | 2017-10-16 15:57:17 -0700 | [diff] [blame] | 267 | /* target cluster/system state */ |
| 268 | return target; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 269 | } |
| 270 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 271 | int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 272 | { |
| 273 | const plat_local_state_t *pwr_domain_state = |
| 274 | target_state->pwr_domain_state; |
| 275 | plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 276 | uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] & |
Varun Wadekar | 362a6b2 | 2017-11-10 11:04:42 -0800 | [diff] [blame] | 277 | TEGRA194_STATE_ID_MASK; |
Steven Kao | 55c2ce7 | 2016-12-23 15:51:32 +0800 | [diff] [blame] | 278 | uint64_t val; |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 279 | u_register_t ns_sctlr_el1; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 280 | |
| 281 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
| 282 | /* |
| 283 | * The TZRAM loses power when we enter system suspend. To |
| 284 | * allow graceful exit from system suspend, we need to copy |
| 285 | * BL3-1 over to TZDRAM. |
| 286 | */ |
| 287 | val = params_from_bl2->tzdram_base + |
Varun Wadekar | e0c222f | 2017-11-10 13:23:34 -0800 | [diff] [blame] | 288 | tegra194_get_cpu_reset_handler_size(); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 289 | memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE, |
| 290 | (uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE); |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 291 | |
Vignesh Radhakrishnan | d7a5c25 | 2017-05-25 16:27:42 -0700 | [diff] [blame] | 292 | /* |
| 293 | * In fake suspend mode, ensure that the loopback procedure |
| 294 | * towards system suspend exit is started, instead of calling |
| 295 | * WFI. This is done by disabling both MMU's of EL1 & El3 |
| 296 | * and calling tegra_secure_entrypoint(). |
| 297 | */ |
| 298 | if (tegra_fake_system_suspend) { |
| 299 | |
| 300 | /* |
| 301 | * Disable EL1's MMU. |
| 302 | */ |
| 303 | ns_sctlr_el1 = read_sctlr_el1(); |
| 304 | ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT)); |
| 305 | write_sctlr_el1(ns_sctlr_el1); |
| 306 | |
| 307 | /* |
| 308 | * Disable MMU to power up the CPU in a "clean" |
| 309 | * state |
| 310 | */ |
| 311 | disable_mmu_el3(); |
| 312 | tegra_secure_entrypoint(); |
| 313 | panic(); |
| 314 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 315 | } |
| 316 | |
| 317 | return PSCI_E_SUCCESS; |
| 318 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 319 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 320 | int32_t tegra_soc_pwr_domain_on(u_register_t mpidr) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 321 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 322 | uint64_t target_cpu = mpidr & MPIDR_CPU_MASK; |
| 323 | uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >> |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 324 | MPIDR_AFFINITY_BITS; |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 325 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 326 | |
Varun Wadekar | a4e0a81 | 2017-10-17 10:53:33 -0700 | [diff] [blame] | 327 | if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 328 | ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr); |
| 329 | return PSCI_E_NOT_PRESENT; |
| 330 | } |
| 331 | |
| 332 | /* construct the target CPU # */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 333 | target_cpu += (target_cluster << 1U); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 334 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 335 | ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U); |
| 336 | if (ret < 0) { |
| 337 | return PSCI_E_DENIED; |
| 338 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 339 | |
| 340 | return PSCI_E_SUCCESS; |
| 341 | } |
| 342 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 343 | int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 344 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 345 | uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 346 | |
| 347 | /* |
| 348 | * Reset power state info for CPUs when onlining, we set |
| 349 | * deepest power when offlining a core but that may not be |
| 350 | * requested by non-secure sw which controls idle states. It |
| 351 | * will re-init this info from non-secure software when the |
| 352 | * core come online. |
| 353 | */ |
| 354 | |
| 355 | /* |
| 356 | * Check if we are exiting from deep sleep and restore SE |
| 357 | * context if we are. |
| 358 | */ |
| 359 | if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { |
Dilan Lee | 4e7a63c | 2017-08-10 16:01:42 +0800 | [diff] [blame] | 360 | |
| 361 | /* |
| 362 | * Enable strict checking after programming the GSC for |
| 363 | * enabling TZSRAM and TZDRAM |
| 364 | */ |
| 365 | mce_enable_strict_checking(); |
| 366 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 367 | /* Init SMMU */ |
Vignesh Radhakrishnan | 978887f | 2017-07-11 15:16:08 -0700 | [diff] [blame] | 368 | tegra_smmu_init(); |
| 369 | |
Steven Kao | 530b217 | 2017-06-23 16:18:58 +0800 | [diff] [blame] | 370 | /* Resume SE, RNG1 and PKA1 */ |
| 371 | tegra_se_resume(); |
| 372 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 373 | /* |
| 374 | * Reset power state info for the last core doing SC7 |
| 375 | * entry and exit, we set deepest power state as CC7 |
| 376 | * and SC7 for SC7 entry which may not be requested by |
| 377 | * non-secure SW which controls idle states. |
| 378 | */ |
| 379 | } |
| 380 | |
| 381 | return PSCI_E_SUCCESS; |
| 382 | } |
| 383 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 384 | int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 385 | { |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 386 | uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 387 | int32_t ret = 0; |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 388 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 389 | (void)target_state; |
| 390 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 391 | /* Disable Denver's DCO operations */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 392 | if (impl == DENVER_IMPL) { |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 393 | denver_disable_dco(); |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 394 | } |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 395 | |
| 396 | /* Turn off CPU */ |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 397 | ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, |
| 398 | (uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U); |
Krishna Sitaraman | 74813f9 | 2017-07-14 13:51:44 -0700 | [diff] [blame] | 399 | assert(ret == 0); |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 400 | |
| 401 | return PSCI_E_SUCCESS; |
| 402 | } |
| 403 | |
| 404 | __dead2 void tegra_soc_prepare_system_off(void) |
| 405 | { |
| 406 | /* System power off */ |
| 407 | |
| 408 | /* SC8 */ |
| 409 | |
| 410 | wfi(); |
| 411 | |
| 412 | /* wait for the system to power down */ |
| 413 | for (;;) { |
| 414 | ; |
| 415 | } |
| 416 | } |
| 417 | |
Anthony Zhou | 8bf6d4e | 2017-09-20 17:44:43 +0800 | [diff] [blame] | 418 | int32_t tegra_soc_prepare_system_reset(void) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 419 | { |
| 420 | return PSCI_E_SUCCESS; |
| 421 | } |