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Achin Gupta1fa7eb62015-11-03 14:18:34 +00001/*
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta1fa7eb62015-11-03 14:18:34 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta1fa7eb62015-11-03 14:18:34 +00005 */
6
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -05007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <platform_def.h>
9
Claus Pedersen785e66c2022-09-12 22:42:58 +000010#include <common/debug.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/interrupt_props.h>
12#include <drivers/arm/gicv3.h>
13#include <lib/utils.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000014#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000015#include <plat/common/platform.h>
16
Achin Gupta1fa7eb62015-11-03 14:18:34 +000017/******************************************************************************
18 * The following functions are defined as weak to allow a platform to override
19 * the way the GICv3 driver is initialised and used.
20 *****************************************************************************/
21#pragma weak plat_arm_gic_driver_init
22#pragma weak plat_arm_gic_init
23#pragma weak plat_arm_gic_cpuif_enable
24#pragma weak plat_arm_gic_cpuif_disable
25#pragma weak plat_arm_gic_pcpu_init
Jeenu Viswambharan78132c92016-12-09 11:12:34 +000026#pragma weak plat_arm_gic_redistif_on
27#pragma weak plat_arm_gic_redistif_off
Achin Gupta1fa7eb62015-11-03 14:18:34 +000028
29/* The GICv3 driver only needs to be initialized in EL3 */
Soby Mathewcf022c52016-01-13 17:06:00 +000030static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
Achin Gupta1fa7eb62015-11-03 14:18:34 +000031
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +053032/* Default GICR base address to be used for GICR probe. */
33static const uintptr_t gicr_base_addrs[2] = {
34 PLAT_ARM_GICR_BASE, /* GICR Base address of the primary CPU */
35 0U /* Zero Termination */
36};
37
38/* List of zero terminated GICR frame addresses which CPUs will probe */
39static const uintptr_t *gicr_frames = gicr_base_addrs;
40
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010041static const interrupt_prop_t arm_interrupt_props[] = {
42 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
43 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000044};
45
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000046/*
Soby Mathew9ca28062017-10-11 16:08:58 +010047 * We save and restore the GICv3 context on system suspend. Allocate the
Ambroise Vincent67dd93e2019-07-18 10:56:14 +010048 * data in the designated EL3 Secure carve-out memory. The `used` attribute
49 * is used to prevent the compiler from removing the gicv3 contexts.
Soby Mathew9ca28062017-10-11 16:08:58 +010050 */
Chris Kay33bfc5e2023-02-14 11:30:04 +000051static gicv3_redist_ctx_t rdist_ctx __section(".arm_el3_tzc_dram") __used;
52static gicv3_dist_ctx_t dist_ctx __section(".arm_el3_tzc_dram") __used;
Soby Mathew12cdcd22018-10-12 16:26:20 +010053
54/* Define accessor function to get reference to the GICv3 context */
55DEFINE_LOAD_SYM_ADDR(rdist_ctx)
56DEFINE_LOAD_SYM_ADDR(dist_ctx)
Soby Mathew9ca28062017-10-11 16:08:58 +010057
58/*
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000059 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
60 * to core position.
61 *
62 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
63 * values read from GICR_TYPER don't have an MT field. To reuse the same
64 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
65 * that read from GICR_TYPER.
66 *
67 * Assumptions:
68 *
69 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
70 * - No CPUs implemented in the system use affinity level 3.
71 */
72static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
73{
74 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
75 return plat_arm_calc_core_pos(mpidr);
76}
77
Roberto Vargas2ca18d92018-02-12 12:36:17 +000078static const gicv3_driver_data_t arm_gic_data __unused = {
Achin Gupta1fa7eb62015-11-03 14:18:34 +000079 .gicd_base = PLAT_ARM_GICD_BASE,
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -050080 .gicr_base = 0U,
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010081 .interrupt_props = arm_interrupt_props,
82 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
Achin Gupta1fa7eb62015-11-03 14:18:34 +000083 .rdistif_num = PLATFORM_CORE_COUNT,
84 .rdistif_base_addrs = rdistif_base_addrs,
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000085 .mpidr_to_core_pos = arm_gicv3_mpidr_hash
Achin Gupta1fa7eb62015-11-03 14:18:34 +000086};
87
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +053088/*
89 * By default, gicr_frames will be pointing to gicr_base_addrs. If
90 * the platform supports a non-contiguous GICR frames (GICR frames located
91 * at uneven offset), plat_arm_override_gicr_frames function can be used by
92 * such platform to override the gicr_frames.
93 */
94void plat_arm_override_gicr_frames(const uintptr_t *plat_gicr_frames)
95{
96 assert(plat_gicr_frames != NULL);
97 gicr_frames = plat_gicr_frames;
98}
99
Daniel Boulby844b4872018-09-18 13:36:39 +0100100void __init plat_arm_gic_driver_init(void)
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000101{
102 /*
103 * The GICv3 driver is initialized in EL3 and does not need
104 * to be initialized again in SEL1. This is because the S-EL1
105 * can use GIC system registers to manage interrupts and does
106 * not need GIC interface base addresses to be configured.
107 */
Julius Werner8e0ef0f2019-07-09 14:02:43 -0700108#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
109 (defined(__aarch64__) && defined(IMAGE_BL31))
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000110 gicv3_driver_init(&arm_gic_data);
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500111
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530112 if (gicv3_rdistif_probe(gicr_base_addrs[0]) == -1) {
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500113 ERROR("No GICR base frame found for Primary CPU\n");
114 panic();
115 }
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000116#endif
117}
118
119/******************************************************************************
120 * ARM common helper to initialize the GIC. Only invoked by BL31
121 *****************************************************************************/
Daniel Boulby844b4872018-09-18 13:36:39 +0100122void __init plat_arm_gic_init(void)
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000123{
124 gicv3_distif_init();
125 gicv3_rdistif_init(plat_my_core_pos());
126 gicv3_cpuif_enable(plat_my_core_pos());
127}
128
129/******************************************************************************
130 * ARM common helper to enable the GIC CPU interface
131 *****************************************************************************/
132void plat_arm_gic_cpuif_enable(void)
133{
134 gicv3_cpuif_enable(plat_my_core_pos());
135}
136
137/******************************************************************************
138 * ARM common helper to disable the GIC CPU interface
139 *****************************************************************************/
140void plat_arm_gic_cpuif_disable(void)
141{
142 gicv3_cpuif_disable(plat_my_core_pos());
143}
144
145/******************************************************************************
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500146 * ARM common helper function to iterate over all GICR frames and discover the
147 * corresponding per-cpu redistributor frame as well as initialize the
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530148 * corresponding interface in GICv3.
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000149 *****************************************************************************/
150void plat_arm_gic_pcpu_init(void)
151{
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500152 int result;
Vijayenthiran Subramaniam2dfa7642019-10-11 14:01:25 +0530153 const uintptr_t *plat_gicr_frames = gicr_frames;
154
155 do {
156 result = gicv3_rdistif_probe(*plat_gicr_frames);
157
158 /* If the probe is successful, no need to proceed further */
159 if (result == 0)
160 break;
161
162 plat_gicr_frames++;
163 } while (*plat_gicr_frames != 0U);
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500164
Madhukar Pappireddy2859b7d2019-06-10 16:54:36 -0500165 if (result == -1) {
166 ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
167 panic();
168 }
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000169 gicv3_rdistif_init(plat_my_core_pos());
170}
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000171
172/******************************************************************************
173 * ARM common helpers to power GIC redistributor interface
174 *****************************************************************************/
175void plat_arm_gic_redistif_on(void)
176{
177 gicv3_rdistif_on(plat_my_core_pos());
178}
179
180void plat_arm_gic_redistif_off(void)
181{
182 gicv3_rdistif_off(plat_my_core_pos());
183}
Soby Mathew9ca28062017-10-11 16:08:58 +0100184
185/******************************************************************************
186 * ARM common helper to save & restore the GICv3 on resume from system suspend
187 *****************************************************************************/
188void plat_arm_gic_save(void)
189{
Soby Mathew12cdcd22018-10-12 16:26:20 +0100190 gicv3_redist_ctx_t * const rdist_context =
191 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
192 gicv3_dist_ctx_t * const dist_context =
193 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
Soby Mathew9ca28062017-10-11 16:08:58 +0100194
195 /*
196 * If an ITS is available, save its context before
197 * the Redistributor using:
198 * gicv3_its_save_disable(gits_base, &its_ctx[i])
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000199 * Additionally, an implementation-defined sequence may
Soby Mathew9ca28062017-10-11 16:08:58 +0100200 * be required to save the whole ITS state.
201 */
202
203 /*
204 * Save the GIC Redistributors and ITS contexts before the
205 * Distributor context. As we only handle SYSTEM SUSPEND API,
206 * we only need to save the context of the CPU that is issuing
207 * the SYSTEM SUSPEND call, i.e. the current CPU.
208 */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100209 gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100210
211 /* Save the GIC Distributor context */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100212 gicv3_distif_save(dist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100213
214 /*
215 * From here, all the components of the GIC can be safely powered down
216 * as long as there is an alternate way to handle wakeup interrupt
217 * sources.
218 */
219}
220
221void plat_arm_gic_resume(void)
222{
Soby Mathew12cdcd22018-10-12 16:26:20 +0100223 const gicv3_redist_ctx_t *rdist_context =
224 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
225 const gicv3_dist_ctx_t *dist_context =
226 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
227
Soby Mathew9ca28062017-10-11 16:08:58 +0100228 /* Restore the GIC Distributor context */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100229 gicv3_distif_init_restore(dist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100230
231 /*
232 * Restore the GIC Redistributor and ITS contexts after the
233 * Distributor context. As we only handle SYSTEM SUSPEND API,
234 * we only need to restore the context of the CPU that issued
235 * the SYSTEM SUSPEND call.
236 */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100237 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100238
239 /*
240 * If an ITS is available, restore its context after
241 * the Redistributor using:
242 * gicv3_its_restore(gits_base, &its_ctx[i])
243 * An implementation-defined sequence may be required to
244 * restore the whole ITS state. The ITS must also be
245 * re-enabled after this sequence has been executed.
246 */
247}