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Achin Gupta1fa7eb62015-11-03 14:18:34 +00001/*
Roberto Vargas2ca18d92018-02-12 12:36:17 +00002 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta1fa7eb62015-11-03 14:18:34 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta1fa7eb62015-11-03 14:18:34 +00005 */
6
7#include <arm_def.h>
8#include <gicv3.h>
Jeenu Viswambharan723dce02017-09-22 08:59:59 +01009#include <interrupt_props.h>
Achin Gupta1fa7eb62015-11-03 14:18:34 +000010#include <plat_arm.h>
11#include <platform.h>
12#include <platform_def.h>
13
14/******************************************************************************
15 * The following functions are defined as weak to allow a platform to override
16 * the way the GICv3 driver is initialised and used.
17 *****************************************************************************/
18#pragma weak plat_arm_gic_driver_init
19#pragma weak plat_arm_gic_init
20#pragma weak plat_arm_gic_cpuif_enable
21#pragma weak plat_arm_gic_cpuif_disable
22#pragma weak plat_arm_gic_pcpu_init
Jeenu Viswambharan78132c92016-12-09 11:12:34 +000023#pragma weak plat_arm_gic_redistif_on
24#pragma weak plat_arm_gic_redistif_off
Achin Gupta1fa7eb62015-11-03 14:18:34 +000025
26/* The GICv3 driver only needs to be initialized in EL3 */
Soby Mathewcf022c52016-01-13 17:06:00 +000027static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
Achin Gupta1fa7eb62015-11-03 14:18:34 +000028
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010029static const interrupt_prop_t arm_interrupt_props[] = {
30 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
31 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000032};
33
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000034/*
Soby Mathew9ca28062017-10-11 16:08:58 +010035 * We save and restore the GICv3 context on system suspend. Allocate the
36 * data in the designated EL3 Secure carve-out memory
37 */
Roberto Vargas2ca18d92018-02-12 12:36:17 +000038static gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
39static gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
Soby Mathew9ca28062017-10-11 16:08:58 +010040
41/*
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000042 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
43 * to core position.
44 *
45 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
46 * values read from GICR_TYPER don't have an MT field. To reuse the same
47 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
48 * that read from GICR_TYPER.
49 *
50 * Assumptions:
51 *
52 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
53 * - No CPUs implemented in the system use affinity level 3.
54 */
55static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
56{
57 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
58 return plat_arm_calc_core_pos(mpidr);
59}
60
Roberto Vargas2ca18d92018-02-12 12:36:17 +000061static const gicv3_driver_data_t arm_gic_data __unused = {
Achin Gupta1fa7eb62015-11-03 14:18:34 +000062 .gicd_base = PLAT_ARM_GICD_BASE,
63 .gicr_base = PLAT_ARM_GICR_BASE,
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010064 .interrupt_props = arm_interrupt_props,
65 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
Achin Gupta1fa7eb62015-11-03 14:18:34 +000066 .rdistif_num = PLATFORM_CORE_COUNT,
67 .rdistif_base_addrs = rdistif_base_addrs,
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000068 .mpidr_to_core_pos = arm_gicv3_mpidr_hash
Achin Gupta1fa7eb62015-11-03 14:18:34 +000069};
70
71void plat_arm_gic_driver_init(void)
72{
73 /*
74 * The GICv3 driver is initialized in EL3 and does not need
75 * to be initialized again in SEL1. This is because the S-EL1
76 * can use GIC system registers to manage interrupts and does
77 * not need GIC interface base addresses to be configured.
78 */
Masahiro Yamadaa2698372016-12-26 00:22:47 +090079#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
80 (defined(IMAGE_BL31) && !defined(AARCH32))
Achin Gupta1fa7eb62015-11-03 14:18:34 +000081 gicv3_driver_init(&arm_gic_data);
82#endif
83}
84
85/******************************************************************************
86 * ARM common helper to initialize the GIC. Only invoked by BL31
87 *****************************************************************************/
88void plat_arm_gic_init(void)
89{
90 gicv3_distif_init();
91 gicv3_rdistif_init(plat_my_core_pos());
92 gicv3_cpuif_enable(plat_my_core_pos());
93}
94
95/******************************************************************************
96 * ARM common helper to enable the GIC CPU interface
97 *****************************************************************************/
98void plat_arm_gic_cpuif_enable(void)
99{
100 gicv3_cpuif_enable(plat_my_core_pos());
101}
102
103/******************************************************************************
104 * ARM common helper to disable the GIC CPU interface
105 *****************************************************************************/
106void plat_arm_gic_cpuif_disable(void)
107{
108 gicv3_cpuif_disable(plat_my_core_pos());
109}
110
111/******************************************************************************
112 * ARM common helper to initialize the per-cpu redistributor interface in GICv3
113 *****************************************************************************/
114void plat_arm_gic_pcpu_init(void)
115{
116 gicv3_rdistif_init(plat_my_core_pos());
117}
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000118
119/******************************************************************************
120 * ARM common helpers to power GIC redistributor interface
121 *****************************************************************************/
122void plat_arm_gic_redistif_on(void)
123{
124 gicv3_rdistif_on(plat_my_core_pos());
125}
126
127void plat_arm_gic_redistif_off(void)
128{
129 gicv3_rdistif_off(plat_my_core_pos());
130}
Soby Mathew9ca28062017-10-11 16:08:58 +0100131
132/******************************************************************************
133 * ARM common helper to save & restore the GICv3 on resume from system suspend
134 *****************************************************************************/
135void plat_arm_gic_save(void)
136{
137
138 /*
139 * If an ITS is available, save its context before
140 * the Redistributor using:
141 * gicv3_its_save_disable(gits_base, &its_ctx[i])
142 * Additionnaly, an implementation-defined sequence may
143 * be required to save the whole ITS state.
144 */
145
146 /*
147 * Save the GIC Redistributors and ITS contexts before the
148 * Distributor context. As we only handle SYSTEM SUSPEND API,
149 * we only need to save the context of the CPU that is issuing
150 * the SYSTEM SUSPEND call, i.e. the current CPU.
151 */
152 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
153
154 /* Save the GIC Distributor context */
155 gicv3_distif_save(&dist_ctx);
156
157 /*
158 * From here, all the components of the GIC can be safely powered down
159 * as long as there is an alternate way to handle wakeup interrupt
160 * sources.
161 */
162}
163
164void plat_arm_gic_resume(void)
165{
166 /* Restore the GIC Distributor context */
167 gicv3_distif_init_restore(&dist_ctx);
168
169 /*
170 * Restore the GIC Redistributor and ITS contexts after the
171 * Distributor context. As we only handle SYSTEM SUSPEND API,
172 * we only need to restore the context of the CPU that issued
173 * the SYSTEM SUSPEND call.
174 */
175 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
176
177 /*
178 * If an ITS is available, restore its context after
179 * the Redistributor using:
180 * gicv3_its_restore(gits_base, &its_ctx[i])
181 * An implementation-defined sequence may be required to
182 * restore the whole ITS state. The ITS must also be
183 * re-enabled after this sequence has been executed.
184 */
185}