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Achin Gupta1fa7eb62015-11-03 14:18:34 +00001/*
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta1fa7eb62015-11-03 14:18:34 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta1fa7eb62015-11-03 14:18:34 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
9#include <common/interrupt_props.h>
10#include <drivers/arm/gicv3.h>
11#include <lib/utils.h>
12#include <plat/common/platform.h>
13
Achin Gupta1fa7eb62015-11-03 14:18:34 +000014#include <arm_def.h>
Achin Gupta1fa7eb62015-11-03 14:18:34 +000015#include <plat_arm.h>
Achin Gupta1fa7eb62015-11-03 14:18:34 +000016
17/******************************************************************************
18 * The following functions are defined as weak to allow a platform to override
19 * the way the GICv3 driver is initialised and used.
20 *****************************************************************************/
21#pragma weak plat_arm_gic_driver_init
22#pragma weak plat_arm_gic_init
23#pragma weak plat_arm_gic_cpuif_enable
24#pragma weak plat_arm_gic_cpuif_disable
25#pragma weak plat_arm_gic_pcpu_init
Jeenu Viswambharan78132c92016-12-09 11:12:34 +000026#pragma weak plat_arm_gic_redistif_on
27#pragma weak plat_arm_gic_redistif_off
Achin Gupta1fa7eb62015-11-03 14:18:34 +000028
29/* The GICv3 driver only needs to be initialized in EL3 */
Soby Mathewcf022c52016-01-13 17:06:00 +000030static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
Achin Gupta1fa7eb62015-11-03 14:18:34 +000031
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010032static const interrupt_prop_t arm_interrupt_props[] = {
33 PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
34 PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000035};
36
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000037/*
Soby Mathew9ca28062017-10-11 16:08:58 +010038 * We save and restore the GICv3 context on system suspend. Allocate the
Soby Mathew12cdcd22018-10-12 16:26:20 +010039 * data in the designated EL3 Secure carve-out memory. The `volatile`
40 * is used to prevent the compiler from removing the gicv3 contexts even
41 * though the DEFINE_LOAD_SYM_ADDR creates a dummy reference to it.
Soby Mathew9ca28062017-10-11 16:08:58 +010042 */
Soby Mathew12cdcd22018-10-12 16:26:20 +010043static volatile gicv3_redist_ctx_t rdist_ctx __section("arm_el3_tzc_dram");
44static volatile gicv3_dist_ctx_t dist_ctx __section("arm_el3_tzc_dram");
45
46/* Define accessor function to get reference to the GICv3 context */
47DEFINE_LOAD_SYM_ADDR(rdist_ctx)
48DEFINE_LOAD_SYM_ADDR(dist_ctx)
Soby Mathew9ca28062017-10-11 16:08:58 +010049
50/*
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000051 * MPIDR hashing function for translating MPIDRs read from GICR_TYPER register
52 * to core position.
53 *
54 * Calculating core position is dependent on MPIDR_EL1.MT bit. However, affinity
55 * values read from GICR_TYPER don't have an MT field. To reuse the same
56 * translation used for CPUs, we insert MT bit read from the PE's MPIDR into
57 * that read from GICR_TYPER.
58 *
59 * Assumptions:
60 *
61 * - All CPUs implemented in the system have MPIDR_EL1.MT bit set;
62 * - No CPUs implemented in the system use affinity level 3.
63 */
64static unsigned int arm_gicv3_mpidr_hash(u_register_t mpidr)
65{
66 mpidr |= (read_mpidr_el1() & MPIDR_MT_MASK);
67 return plat_arm_calc_core_pos(mpidr);
68}
69
Roberto Vargas2ca18d92018-02-12 12:36:17 +000070static const gicv3_driver_data_t arm_gic_data __unused = {
Achin Gupta1fa7eb62015-11-03 14:18:34 +000071 .gicd_base = PLAT_ARM_GICD_BASE,
72 .gicr_base = PLAT_ARM_GICR_BASE,
Jeenu Viswambharan723dce02017-09-22 08:59:59 +010073 .interrupt_props = arm_interrupt_props,
74 .interrupt_props_num = ARRAY_SIZE(arm_interrupt_props),
Achin Gupta1fa7eb62015-11-03 14:18:34 +000075 .rdistif_num = PLATFORM_CORE_COUNT,
76 .rdistif_base_addrs = rdistif_base_addrs,
Jeenu Viswambharan528d21b2016-11-15 13:53:57 +000077 .mpidr_to_core_pos = arm_gicv3_mpidr_hash
Achin Gupta1fa7eb62015-11-03 14:18:34 +000078};
79
Daniel Boulby844b4872018-09-18 13:36:39 +010080void __init plat_arm_gic_driver_init(void)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000081{
82 /*
83 * The GICv3 driver is initialized in EL3 and does not need
84 * to be initialized again in SEL1. This is because the S-EL1
85 * can use GIC system registers to manage interrupts and does
86 * not need GIC interface base addresses to be configured.
87 */
Masahiro Yamadaa2698372016-12-26 00:22:47 +090088#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
89 (defined(IMAGE_BL31) && !defined(AARCH32))
Achin Gupta1fa7eb62015-11-03 14:18:34 +000090 gicv3_driver_init(&arm_gic_data);
91#endif
92}
93
94/******************************************************************************
95 * ARM common helper to initialize the GIC. Only invoked by BL31
96 *****************************************************************************/
Daniel Boulby844b4872018-09-18 13:36:39 +010097void __init plat_arm_gic_init(void)
Achin Gupta1fa7eb62015-11-03 14:18:34 +000098{
99 gicv3_distif_init();
100 gicv3_rdistif_init(plat_my_core_pos());
101 gicv3_cpuif_enable(plat_my_core_pos());
102}
103
104/******************************************************************************
105 * ARM common helper to enable the GIC CPU interface
106 *****************************************************************************/
107void plat_arm_gic_cpuif_enable(void)
108{
109 gicv3_cpuif_enable(plat_my_core_pos());
110}
111
112/******************************************************************************
113 * ARM common helper to disable the GIC CPU interface
114 *****************************************************************************/
115void plat_arm_gic_cpuif_disable(void)
116{
117 gicv3_cpuif_disable(plat_my_core_pos());
118}
119
120/******************************************************************************
121 * ARM common helper to initialize the per-cpu redistributor interface in GICv3
122 *****************************************************************************/
123void plat_arm_gic_pcpu_init(void)
124{
125 gicv3_rdistif_init(plat_my_core_pos());
126}
Jeenu Viswambharan78132c92016-12-09 11:12:34 +0000127
128/******************************************************************************
129 * ARM common helpers to power GIC redistributor interface
130 *****************************************************************************/
131void plat_arm_gic_redistif_on(void)
132{
133 gicv3_rdistif_on(plat_my_core_pos());
134}
135
136void plat_arm_gic_redistif_off(void)
137{
138 gicv3_rdistif_off(plat_my_core_pos());
139}
Soby Mathew9ca28062017-10-11 16:08:58 +0100140
141/******************************************************************************
142 * ARM common helper to save & restore the GICv3 on resume from system suspend
143 *****************************************************************************/
144void plat_arm_gic_save(void)
145{
Soby Mathew12cdcd22018-10-12 16:26:20 +0100146 gicv3_redist_ctx_t * const rdist_context =
147 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
148 gicv3_dist_ctx_t * const dist_context =
149 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
Soby Mathew9ca28062017-10-11 16:08:58 +0100150
151 /*
152 * If an ITS is available, save its context before
153 * the Redistributor using:
154 * gicv3_its_save_disable(gits_base, &its_ctx[i])
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000155 * Additionally, an implementation-defined sequence may
Soby Mathew9ca28062017-10-11 16:08:58 +0100156 * be required to save the whole ITS state.
157 */
158
159 /*
160 * Save the GIC Redistributors and ITS contexts before the
161 * Distributor context. As we only handle SYSTEM SUSPEND API,
162 * we only need to save the context of the CPU that is issuing
163 * the SYSTEM SUSPEND call, i.e. the current CPU.
164 */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100165 gicv3_rdistif_save(plat_my_core_pos(), rdist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100166
167 /* Save the GIC Distributor context */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100168 gicv3_distif_save(dist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100169
170 /*
171 * From here, all the components of the GIC can be safely powered down
172 * as long as there is an alternate way to handle wakeup interrupt
173 * sources.
174 */
175}
176
177void plat_arm_gic_resume(void)
178{
Soby Mathew12cdcd22018-10-12 16:26:20 +0100179 const gicv3_redist_ctx_t *rdist_context =
180 (gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
181 const gicv3_dist_ctx_t *dist_context =
182 (gicv3_dist_ctx_t *)LOAD_ADDR_OF(dist_ctx);
183
Soby Mathew9ca28062017-10-11 16:08:58 +0100184 /* Restore the GIC Distributor context */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100185 gicv3_distif_init_restore(dist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100186
187 /*
188 * Restore the GIC Redistributor and ITS contexts after the
189 * Distributor context. As we only handle SYSTEM SUSPEND API,
190 * we only need to restore the context of the CPU that issued
191 * the SYSTEM SUSPEND call.
192 */
Soby Mathew12cdcd22018-10-12 16:26:20 +0100193 gicv3_rdistif_init_restore(plat_my_core_pos(), rdist_context);
Soby Mathew9ca28062017-10-11 16:08:58 +0100194
195 /*
196 * If an ITS is available, restore its context after
197 * the Redistributor using:
198 * gicv3_its_restore(gits_base, &its_ctx[i])
199 * An implementation-defined sequence may be required to
200 * restore the whole ITS state. The ITS must also be
201 * re-enabled after this sequence has been executed.
202 */
203}