Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 1 | /* |
Bipin Ravi | 8ca7aba | 2023-12-20 15:40:44 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2024, Arm Limited. All rights reserved. |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a78c.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
| 17 | #error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 18 | #endif |
| 19 | |
Govindraj Raja | a4c473e | 2023-06-15 11:32:07 -0500 | [diff] [blame] | 20 | #if WORKAROUND_CVE_2022_23960 |
| 21 | wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c |
| 22 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 23 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 24 | workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430 |
Bipin Ravi | bf205fc | 2023-03-14 10:04:23 -0500 | [diff] [blame] | 25 | /* Disable allocation of splintered pages in the L2 TLB */ |
Govindraj Raja | f37b287 | 2023-06-15 11:57:16 -0500 | [diff] [blame] | 26 | sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 27 | workaround_reset_end cortex_a78c, ERRATUM(1827430) |
Bipin Ravi | bf205fc | 2023-03-14 10:04:23 -0500 | [diff] [blame] | 28 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 29 | check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0) |
Bipin Ravi | e49c704 | 2023-03-14 11:03:24 -0500 | [diff] [blame] | 30 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 31 | workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440 |
Bipin Ravi | e49c704 | 2023-03-14 11:03:24 -0500 | [diff] [blame] | 32 | /* Force Atomic Store to WB memory be done in L1 data cache */ |
Govindraj Raja | f37b287 | 2023-06-15 11:57:16 -0500 | [diff] [blame] | 33 | sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2) |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 34 | workaround_reset_end cortex_a78c, ERRATUM(1827440) |
Bipin Ravi | e49c704 | 2023-03-14 11:03:24 -0500 | [diff] [blame] | 35 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 36 | check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0) |
Bipin Ravi | e49c704 | 2023-03-14 11:03:24 -0500 | [diff] [blame] | 37 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 38 | workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064 |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 39 | /* -------------------------------------------------------- |
| 40 | * Place the data prefetcher in the most conservative mode |
| 41 | * to reduce prefetches by writing the following bits to |
| 42 | * the value indicated: ecltr[7:6], PF_MODE = 2'b11 |
| 43 | * -------------------------------------------------------- |
| 44 | */ |
Govindraj Raja | f37b287 | 2023-06-15 11:57:16 -0500 | [diff] [blame] | 45 | sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7) |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 46 | workaround_reset_end cortex_a78c, ERRATUM(2132064) |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 47 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 48 | check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2) |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 49 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 50 | workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638 |
Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 51 | ldr x0, =0x5 |
| 52 | msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 |
| 53 | ldr x0, =0x10F600E000 |
| 54 | msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 |
| 55 | ldr x0, =0x10FF80E000 |
| 56 | msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 |
| 57 | ldr x0, =0x80000000003FF |
| 58 | msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 59 | workaround_reset_end cortex_a78c, ERRATUM(2242638) |
Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 60 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 61 | check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2) |
Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 62 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 63 | workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749 |
Govindraj Raja | f37b287 | 2023-06-15 11:57:16 -0500 | [diff] [blame] | 64 | sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0 |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 65 | workaround_reset_end cortex_a78c, ERRATUM(2376749) |
Govindraj Raja | a4c473e | 2023-06-15 11:32:07 -0500 | [diff] [blame] | 66 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 67 | check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2) |
Govindraj Raja | a4c473e | 2023-06-15 11:32:07 -0500 | [diff] [blame] | 68 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 69 | workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411 |
Govindraj Raja | f37b287 | 2023-06-15 11:57:16 -0500 | [diff] [blame] | 70 | sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40 |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 71 | workaround_reset_end cortex_a78c, ERRATUM(2395411) |
Govindraj Raja | a4c473e | 2023-06-15 11:32:07 -0500 | [diff] [blame] | 72 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 73 | check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2) |
Govindraj Raja | a4c473e | 2023-06-15 11:32:07 -0500 | [diff] [blame] | 74 | |
Bipin Ravi | 8ca7aba | 2023-12-20 15:40:44 -0600 | [diff] [blame] | 75 | workaround_reset_start cortex_a78c, ERRATUM(2683027), ERRATA_A78C_2683027 |
| 76 | ldr x0, =0x3 |
| 77 | msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 |
| 78 | ldr x0, =0xEE010F10 |
| 79 | msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 |
| 80 | ldr x0, =0xFF1F0FFE |
| 81 | msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 |
| 82 | ldr x0, =0x100000004003FF |
| 83 | msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 |
| 84 | workaround_reset_end cortex_a78c, ERRATUM(2683027) |
| 85 | |
| 86 | check_erratum_range cortex_a78c, ERRATUM(2683027), CPU_REV(0, 1), CPU_REV(0, 2) |
| 87 | |
Sona Mathew | dfde504 | 2023-11-14 14:00:48 -0600 | [diff] [blame] | 88 | workaround_reset_start cortex_a78c, ERRATUM(2743232), ERRATA_A78C_2743232 |
| 89 | /* Set CPUACTLR5_EL1[56:55] to 2'b01 */ |
| 90 | sysreg_bit_set CORTEX_A78C_ACTLR5_EL1, BIT(55) |
| 91 | sysreg_bit_clear CORTEX_A78C_ACTLR5_EL1, BIT(56) |
| 92 | workaround_reset_end cortex_a78c, ERRATUM(2743232) |
| 93 | |
| 94 | check_erratum_range cortex_a78c, ERRATUM(2743232), CPU_REV(0, 1), CPU_REV(0, 2) |
| 95 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 96 | workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 |
Bipin Ravi | e0b52cc | 2023-01-18 11:03:21 -0600 | [diff] [blame] | 97 | /* dsb before isb of power down sequence */ |
| 98 | dsb sy |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 99 | workaround_runtime_end cortex_a78c, ERRATUM(2772121) |
Bipin Ravi | e0b52cc | 2023-01-18 11:03:21 -0600 | [diff] [blame] | 100 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 101 | check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2) |
Bipin Ravi | db09108 | 2023-02-28 16:21:51 -0600 | [diff] [blame] | 102 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 103 | workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484 |
Govindraj Raja | f37b287 | 2023-06-15 11:57:16 -0500 | [diff] [blame] | 104 | sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47) |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 105 | workaround_reset_end cortex_a78c, ERRATUM(2779484) |
Bipin Ravi | db09108 | 2023-02-28 16:21:51 -0600 | [diff] [blame] | 106 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 107 | check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2) |
Bipin Ravi | bf205fc | 2023-03-14 10:04:23 -0500 | [diff] [blame] | 108 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 109 | check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
Bipin Ravi | e49c704 | 2023-03-14 11:03:24 -0500 | [diff] [blame] | 110 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 111 | workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 112 | #if IMAGE_BL31 |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 113 | /* |
| 114 | * The Cortex-A78c generic vectors are overridden to apply errata |
| 115 | * mitigation on exception entry from lower ELs. |
| 116 | */ |
Govindraj Raja | f37b287 | 2023-06-15 11:57:16 -0500 | [diff] [blame] | 117 | override_vector_table wa_cve_vbar_cortex_a78c |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 118 | #endif /* IMAGE_BL31 */ |
| 119 | workaround_reset_end cortex_a78c, CVE(2022, 23960) |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 120 | |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 121 | cpu_reset_func_start cortex_a78c |
| 122 | cpu_reset_func_end cortex_a78c |
| 123 | |
| 124 | errata_report_shim cortex_a78c |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 125 | |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 126 | /* ---------------------------------------------------- |
| 127 | * HW will do the cache maintenance while powering down |
| 128 | * ---------------------------------------------------- |
| 129 | */ |
| 130 | func cortex_a78c_core_pwr_dwn |
| 131 | /* --------------------------------------------------- |
| 132 | * Enable CPU power down bit in power control register |
| 133 | * --------------------------------------------------- |
| 134 | */ |
Govindraj Raja | f37b287 | 2023-06-15 11:57:16 -0500 | [diff] [blame] | 135 | sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
Govindraj Raja | 20a9295 | 2023-06-15 11:47:33 -0500 | [diff] [blame] | 136 | |
| 137 | apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121 |
| 138 | |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 139 | isb |
| 140 | ret |
| 141 | endfunc cortex_a78c_core_pwr_dwn |
| 142 | |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 143 | /* --------------------------------------------- |
| 144 | * This function provides cortex_a78c specific |
| 145 | * register information for crash reporting. |
| 146 | * It needs to return with x6 pointing to |
| 147 | * a list of register names in ascii and |
| 148 | * x8 - x15 having values of registers to be |
| 149 | * reported. |
| 150 | * --------------------------------------------- |
| 151 | */ |
| 152 | .section .rodata.cortex_a78c_regs, "aS" |
| 153 | cortex_a78c_regs: /* The ascii list of register names to be reported */ |
| 154 | .asciz "cpuectlr_el1", "" |
| 155 | |
| 156 | func cortex_a78c_cpu_reg_dump |
| 157 | adr x6, cortex_a78c_regs |
| 158 | mrs x8, CORTEX_A78C_CPUECTLR_EL1 |
| 159 | ret |
| 160 | endfunc cortex_a78c_cpu_reg_dump |
| 161 | |
| 162 | declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 163 | cortex_a78c_reset_func, \ |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 164 | cortex_a78c_core_pwr_dwn |