| commit | e49c704b33ebe50e27f6ef9422de6e43b2f458d3 | [log] [tgz] |
|---|---|---|
| author | Bipin Ravi <bipin.ravi@arm.com> | Tue Mar 14 11:03:24 2023 -0500 |
| committer | Bipin Ravi <bipin.ravi@arm.com> | Tue Mar 21 16:21:38 2023 -0500 |
| tree | 15e2815f02bb2f4847bda4e041b3c83eae26fc3a | |
| parent | bf205fc5f2c16e5bd8bb4f7da25ba8df8ce5a56b [diff] |
fix(cpus): workaround for Cortex-A78C erratum 1827440 Cortex-A78C erratum 1827440 is a Cat B erratum that applies to revision r0p0 and is fixed in r0p1. The workaround is to set CPUACTLR2_EL1[2], which forces atomic store operations to write-back memory to be performed in the L1 data cache. SDEN documentation: https://developer.arm.com/documentation/SDEN1707916/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I41d8ef48f70216ec66bf2b0f4f03ea8d8c261ee7