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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Varun Wadekarb8776152016-03-03 13:52:52 -08002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05303 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Varun Wadekarcad7b082015-12-28 18:12:59 -080031#include <arch_helpers.h>
32#include <assert.h>
Varun Wadekar94701ff2016-05-23 11:47:34 -070033#include <bl31.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080034#include <bl_common.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053035#include <console.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080036#include <context.h>
37#include <context_mgmt.h>
Varun Wadekar4debe052016-05-18 13:39:16 -070038#include <cortex_a57.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080039#include <debug.h>
40#include <denver.h>
41#include <interrupt_mgmt.h>
Varun Wadekar47ddd002016-03-28 16:00:02 -070042#include <mce.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080043#include <platform.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053044#include <tegra_def.h>
Varun Wadekar5887c102016-07-19 11:29:40 -070045#include <tegra_platform.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080046#include <tegra_private.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053047#include <xlat_tables.h>
48
Varun Wadekar4debe052016-05-18 13:39:16 -070049DEFINE_RENAME_SYSREG_RW_FUNCS(l2ctlr_el1, L2CTLR_EL1)
50extern uint64_t tegra_enable_l2_ecc_parity_prot;
51
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080052/*******************************************************************************
53 * The Tegra power domain tree has a single system level power domain i.e. a
54 * single root node. The first entry in the power domain descriptor specifies
55 * the number of power domains at the highest power level.
56 *******************************************************************************
57 */
58const unsigned char tegra_power_domain_tree_desc[] = {
59 /* No of root nodes */
60 1,
61 /* No of clusters */
62 PLATFORM_CLUSTER_COUNT,
63 /* No of CPU cores - cluster0 */
64 PLATFORM_MAX_CPUS_PER_CLUSTER,
65 /* No of CPU cores - cluster1 */
66 PLATFORM_MAX_CPUS_PER_CLUSTER
67};
68
Varun Wadekar921b9062015-08-25 17:03:14 +053069/*
70 * Table of regions to map using the MMU.
71 */
72static const mmap_region_t tegra_mmap[] = {
73 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
74 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekara0f26972016-03-11 17:18:51 -080075 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
76 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053077 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
78 MT_DEVICE | MT_RW | MT_SECURE),
79 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
80 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar9db0ad12016-07-12 10:04:28 -070081 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
82 MT_DEVICE | MT_RW | MT_SECURE),
83 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
84 MT_DEVICE | MT_RW | MT_SECURE),
85 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
Varun Wadekar921b9062015-08-25 17:03:14 +053086 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar4debe052016-05-18 13:39:16 -070087 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
88 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053089 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
90 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -080091 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
92 MT_DEVICE | MT_RW | MT_SECURE),
93 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
94 MT_DEVICE | MT_RW | MT_SECURE),
95 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
96 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekare60f1bf2016-02-17 10:10:50 -080097 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
98 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +053099 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
100 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -0800101 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
102 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +0530103 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
104 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekarb8776152016-03-03 13:52:52 -0800105 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x1000000, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +0530106 MT_DEVICE | MT_RW | MT_SECURE),
107 {0}
108};
109
110/*******************************************************************************
111 * Set up the pagetables as per the platform memory map & initialize the MMU
112 ******************************************************************************/
113const mmap_region_t *plat_get_mmio_map(void)
114{
115 /* MMIO space */
116 return tegra_mmap;
117}
118
119/*******************************************************************************
120 * Handler to get the System Counter Frequency
121 ******************************************************************************/
Varun Wadekaref8a4fe2016-06-02 14:26:13 -0700122unsigned int plat_get_syscnt_freq2(void)
Varun Wadekar921b9062015-08-25 17:03:14 +0530123{
Varun Wadekar20c94292016-01-04 10:57:45 -0800124 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +0530125}
126
127/*******************************************************************************
128 * Maximum supported UART controllers
129 ******************************************************************************/
130#define TEGRA186_MAX_UART_PORTS 7
131
132/*******************************************************************************
133 * This variable holds the UART port base addresses
134 ******************************************************************************/
135static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
136 0, /* undefined - treated as an error case */
137 TEGRA_UARTA_BASE,
138 TEGRA_UARTB_BASE,
139 TEGRA_UARTC_BASE,
140 TEGRA_UARTD_BASE,
141 TEGRA_UARTE_BASE,
142 TEGRA_UARTF_BASE,
143 TEGRA_UARTG_BASE,
144};
145
146/*******************************************************************************
147 * Retrieve the UART controller base to be used as the console
148 ******************************************************************************/
149uint32_t plat_get_console_from_id(int id)
150{
151 if (id > TEGRA186_MAX_UART_PORTS)
152 return 0;
153
154 return tegra186_uart_addresses[id];
155}
Varun Wadekarcad7b082015-12-28 18:12:59 -0800156
Varun Wadekar4debe052016-05-18 13:39:16 -0700157/* represent chip-version as concatenation of major (15:12), minor (11:8) and subrev (7:0) */
158#define TEGRA186_VER_A02P 0x1201
159
160/*******************************************************************************
161 * Handler for early platform setup
162 ******************************************************************************/
163void plat_early_platform_setup(void)
164{
165 int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
Varun Wadekar5887c102016-07-19 11:29:40 -0700166 uint32_t chip_subrev, val;
Varun Wadekar4debe052016-05-18 13:39:16 -0700167
168 /* sanity check MCE firmware compatibility */
169 mce_verify_firmware_version();
170
171 /*
172 * Enable ECC and Parity Protection for Cortex-A57 CPUs
173 * for Tegra A02p SKUs
174 */
175 if (impl != DENVER_IMPL) {
176
177 /* get the major, minor and sub-version values */
Varun Wadekar4debe052016-05-18 13:39:16 -0700178 chip_subrev = mmio_read_32(TEGRA_FUSE_BASE + OPT_SUBREVISION) &
179 SUBREVISION_MASK;
180
181 /* prepare chip version number */
Varun Wadekar5887c102016-07-19 11:29:40 -0700182 val = (tegra_get_chipid_major() << 12) |
183 (tegra_get_chipid_minor() << 8) |
184 chip_subrev;
Varun Wadekar4debe052016-05-18 13:39:16 -0700185
186 /* enable L2 ECC for Tegra186 A02P and beyond */
187 if (val >= TEGRA186_VER_A02P) {
188
189 val = read_l2ctlr_el1();
190 val |= L2_ECC_PARITY_PROTECTION_BIT;
191 write_l2ctlr_el1(val);
192
193 /*
194 * Set the flag to enable ECC/Parity Protection
195 * when we exit System Suspend or Cluster Powerdn
196 */
197 tegra_enable_l2_ecc_parity_prot = 1;
198 }
199 }
200}
201
Varun Wadekarcad7b082015-12-28 18:12:59 -0800202/* Secure IRQs for Tegra186 */
203static const irq_sec_cfg_t tegra186_sec_irqs[] = {
204 {
205 TEGRA186_TOP_WDT_IRQ,
206 TEGRA186_SEC_IRQ_TARGET_MASK,
207 INTR_TYPE_EL3,
208 },
209 {
210 TEGRA186_AON_WDT_IRQ,
211 TEGRA186_SEC_IRQ_TARGET_MASK,
212 INTR_TYPE_EL3,
213 },
214};
215
216/*******************************************************************************
217 * Initialize the GIC and SGIs
218 ******************************************************************************/
219void plat_gic_setup(void)
220{
221 tegra_gic_setup(tegra186_sec_irqs,
222 sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
223
224 /*
225 * Initialize the FIQ handler only if the platform supports any
226 * FIQ interrupt sources.
227 */
228 if (sizeof(tegra186_sec_irqs) > 0)
229 tegra_fiq_handler_setup();
230}
Varun Wadekar94701ff2016-05-23 11:47:34 -0700231
232/*******************************************************************************
233 * Return pointer to the BL31 params from previous bootloader
234 ******************************************************************************/
235bl31_params_t *plat_get_bl31_params(void)
236{
237 uint32_t val;
238
239 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
240
241 return (bl31_params_t *)(uintptr_t)val;
242}
243
244/*******************************************************************************
245 * Return pointer to the BL31 platform params from previous bootloader
246 ******************************************************************************/
247plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
248{
249 uint32_t val;
250
251 val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
252
253 return (plat_params_from_bl2_t *)(uintptr_t)val;
254}