dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 1 | /* |
Roberto Vargas | 2b36b15 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Andre Przywara | c7d10e3 | 2020-10-16 12:06:57 +0100 | [diff] [blame] | 7 | #include <arm_acle.h> |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 8 | #include <assert.h> |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 9 | #include <stdbool.h> |
| 10 | #include <stdint.h> |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 11 | #include <string.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <lib/mmio.h> |
| 14 | #include <lib/utils_def.h> |
Antonio Nino Diaz | a320ecd | 2019-01-15 14:19:50 +0000 | [diff] [blame] | 15 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | |
Andre Przywara | 31ed470 | 2020-10-08 00:45:22 +0100 | [diff] [blame^] | 17 | #include <lib/smccc.h> |
| 18 | #include <services/trng_svc.h> |
| 19 | #include <smccc_helpers.h> |
| 20 | |
| 21 | #include <plat/common/platform.h> |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 22 | |
| 23 | #define NSAMPLE_CLOCKS 1 /* min 1 cycle, max 231 cycles */ |
| 24 | #define NRETRIES 5 |
| 25 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 26 | /* initialised to false */ |
| 27 | static bool juno_trng_initialized; |
| 28 | |
| 29 | static bool output_valid(void) |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 30 | { |
| 31 | int i; |
| 32 | |
| 33 | for (i = 0; i < NRETRIES; i++) { |
| 34 | uint32_t val; |
| 35 | |
| 36 | val = mmio_read_32(TRNG_BASE + TRNG_STATUS); |
| 37 | if (val & 1U) |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 38 | return true; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 39 | } |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 40 | return false; /* No output data available. */ |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 41 | } |
| 42 | |
Andre Przywara | 31ed470 | 2020-10-08 00:45:22 +0100 | [diff] [blame^] | 43 | DEFINE_SVC_UUID2(_plat_trng_uuid, |
| 44 | 0x23523c58, 0x7448, 0x4083, 0x9d, 0x16, |
| 45 | 0xe3, 0xfa, 0xb9, 0xf1, 0x73, 0xbc |
| 46 | ); |
| 47 | uuid_t plat_trng_uuid; |
| 48 | |
Andre Przywara | c7d10e3 | 2020-10-16 12:06:57 +0100 | [diff] [blame] | 49 | static uint32_t crc_value = ~0U; |
| 50 | |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 51 | /* |
Andre Przywara | 31ed470 | 2020-10-08 00:45:22 +0100 | [diff] [blame^] | 52 | * Uses the Trusted Entropy Source peripheral on Juno to return 8 bytes of |
| 53 | * entropy. Returns 'true' when done successfully, 'false' otherwise. |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 54 | */ |
Andre Przywara | 31ed470 | 2020-10-08 00:45:22 +0100 | [diff] [blame^] | 55 | bool plat_get_entropy(uint64_t *out) |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 56 | { |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 57 | uint64_t ret; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 58 | |
Andre Przywara | 31ed470 | 2020-10-08 00:45:22 +0100 | [diff] [blame^] | 59 | assert(out); |
| 60 | assert(!check_uptr_overflow((uintptr_t)out, sizeof(*out))); |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 61 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 62 | if (!juno_trng_initialized) { |
| 63 | /* Disable interrupt mode. */ |
| 64 | mmio_write_32(TRNG_BASE + TRNG_INTMASK, 0); |
| 65 | /* Program TRNG to sample for `NSAMPLE_CLOCKS`. */ |
| 66 | mmio_write_32(TRNG_BASE + TRNG_CONFIG, NSAMPLE_CLOCKS); |
| 67 | /* Abort any potentially pending sampling. */ |
| 68 | mmio_write_32(TRNG_BASE + TRNG_CONTROL, 2); |
| 69 | /* Reset TRNG outputs. */ |
| 70 | mmio_write_32(TRNG_BASE + TRNG_STATUS, 1); |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 71 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 72 | juno_trng_initialized = true; |
| 73 | } |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 74 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 75 | if (!output_valid()) { |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 76 | /* Start TRNG. */ |
| 77 | mmio_write_32(TRNG_BASE + TRNG_CONTROL, 1); |
| 78 | |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 79 | if (!output_valid()) |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 80 | return false; |
| 81 | } |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 82 | |
Andre Przywara | c7d10e3 | 2020-10-16 12:06:57 +0100 | [diff] [blame] | 83 | /* CRC each two 32-bit registers together, combine the pairs */ |
| 84 | crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 0)); |
| 85 | crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 4)); |
| 86 | ret = (uint64_t)crc_value << 32; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 87 | |
Andre Przywara | c7d10e3 | 2020-10-16 12:06:57 +0100 | [diff] [blame] | 88 | crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 8)); |
| 89 | crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 12)); |
Andre Przywara | 31ed470 | 2020-10-08 00:45:22 +0100 | [diff] [blame^] | 90 | *out = ret | crc_value; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 91 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 92 | /* Acknowledge current cycle, clear output registers. */ |
| 93 | mmio_write_32(TRNG_BASE + TRNG_STATUS, 1); |
| 94 | /* Trigger next TRNG cycle. */ |
| 95 | mmio_write_32(TRNG_BASE + TRNG_CONTROL, 1); |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 96 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 97 | return true; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 98 | } |
Andre Przywara | 31ed470 | 2020-10-08 00:45:22 +0100 | [diff] [blame^] | 99 | |
| 100 | void plat_entropy_setup(void) |
| 101 | { |
| 102 | uint64_t dummy; |
| 103 | |
| 104 | plat_trng_uuid = _plat_trng_uuid; |
| 105 | |
| 106 | /* Initialise the entropy source and trigger RNG generation */ |
| 107 | plat_get_entropy(&dummy); |
| 108 | } |