dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 1 | /* |
Roberto Vargas | 2b36b15 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 2 | * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
Andre Przywara | c7d10e3 | 2020-10-16 12:06:57 +0100 | [diff] [blame^] | 7 | #include <arm_acle.h> |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 8 | #include <assert.h> |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 9 | #include <stdbool.h> |
| 10 | #include <stdint.h> |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 11 | #include <string.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | |
| 13 | #include <lib/mmio.h> |
| 14 | #include <lib/utils_def.h> |
Antonio Nino Diaz | a320ecd | 2019-01-15 14:19:50 +0000 | [diff] [blame] | 15 | #include <platform_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | |
Roberto Vargas | 2b36b15 | 2018-02-12 12:36:17 +0000 | [diff] [blame] | 17 | #include "juno_decl.h" |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 18 | |
| 19 | #define NSAMPLE_CLOCKS 1 /* min 1 cycle, max 231 cycles */ |
| 20 | #define NRETRIES 5 |
| 21 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 22 | /* initialised to false */ |
| 23 | static bool juno_trng_initialized; |
| 24 | |
| 25 | static bool output_valid(void) |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 26 | { |
| 27 | int i; |
| 28 | |
| 29 | for (i = 0; i < NRETRIES; i++) { |
| 30 | uint32_t val; |
| 31 | |
| 32 | val = mmio_read_32(TRNG_BASE + TRNG_STATUS); |
| 33 | if (val & 1U) |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 34 | return true; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 35 | } |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 36 | return false; /* No output data available. */ |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 37 | } |
| 38 | |
Andre Przywara | c7d10e3 | 2020-10-16 12:06:57 +0100 | [diff] [blame^] | 39 | static uint32_t crc_value = ~0U; |
| 40 | |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 41 | /* |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 42 | * This function fills `buf` with 8 bytes of entropy. |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 43 | * It uses the Trusted Entropy Source peripheral on Juno. |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 44 | * Returns 'true' when the buffer has been filled with entropy |
| 45 | * successfully, or 'false' otherwise. |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 46 | */ |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 47 | bool juno_getentropy(uint64_t *buf) |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 48 | { |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 49 | uint64_t ret; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 50 | |
| 51 | assert(buf); |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 52 | assert(!check_uptr_overflow((uintptr_t)buf, sizeof(*buf))); |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 53 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 54 | if (!juno_trng_initialized) { |
| 55 | /* Disable interrupt mode. */ |
| 56 | mmio_write_32(TRNG_BASE + TRNG_INTMASK, 0); |
| 57 | /* Program TRNG to sample for `NSAMPLE_CLOCKS`. */ |
| 58 | mmio_write_32(TRNG_BASE + TRNG_CONFIG, NSAMPLE_CLOCKS); |
| 59 | /* Abort any potentially pending sampling. */ |
| 60 | mmio_write_32(TRNG_BASE + TRNG_CONTROL, 2); |
| 61 | /* Reset TRNG outputs. */ |
| 62 | mmio_write_32(TRNG_BASE + TRNG_STATUS, 1); |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 63 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 64 | juno_trng_initialized = true; |
| 65 | } |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 66 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 67 | if (!output_valid()) { |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 68 | /* Start TRNG. */ |
| 69 | mmio_write_32(TRNG_BASE + TRNG_CONTROL, 1); |
| 70 | |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 71 | if (!output_valid()) |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 72 | return false; |
| 73 | } |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 74 | |
Andre Przywara | c7d10e3 | 2020-10-16 12:06:57 +0100 | [diff] [blame^] | 75 | /* CRC each two 32-bit registers together, combine the pairs */ |
| 76 | crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 0)); |
| 77 | crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 4)); |
| 78 | ret = (uint64_t)crc_value << 32; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 79 | |
Andre Przywara | c7d10e3 | 2020-10-16 12:06:57 +0100 | [diff] [blame^] | 80 | crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 8)); |
| 81 | crc_value = __crc32w(crc_value, mmio_read_32(TRNG_BASE + 12)); |
| 82 | *buf = ret | crc_value; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 83 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 84 | /* Acknowledge current cycle, clear output registers. */ |
| 85 | mmio_write_32(TRNG_BASE + TRNG_STATUS, 1); |
| 86 | /* Trigger next TRNG cycle. */ |
| 87 | mmio_write_32(TRNG_BASE + TRNG_CONTROL, 1); |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 88 | |
Andre Przywara | 927b399 | 2020-10-08 00:43:50 +0100 | [diff] [blame] | 89 | return true; |
dp-arm | 8f59e15 | 2017-02-27 12:21:43 +0000 | [diff] [blame] | 90 | } |