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John Tsichritzis4daa1de2018-07-23 09:11:59 +01001/*
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +00002 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
John Tsichritzis4daa1de2018-07-23 09:11:59 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef DSU_DEF_H
8#define DSU_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/utils_def.h>
John Tsichritzis4daa1de2018-07-23 09:11:59 +010011
12/********************************************************************
Louis Mayencourt254f6f02019-04-09 14:11:06 +010013 * DSU Cluster Configuration registers definitions
John Tsichritzis4daa1de2018-07-23 09:11:59 +010014 ********************************************************************/
15#define CLUSTERCFR_EL1 S3_0_C15_C3_0
Louis Mayencourt254f6f02019-04-09 14:11:06 +010016
17#define CLUSTERCFR_ACP_SHIFT U(11)
John Tsichritzis4daa1de2018-07-23 09:11:59 +010018
19/********************************************************************
Louis Mayencourt254f6f02019-04-09 14:11:06 +010020 * DSU Cluster Main Revision ID registers definitions
John Tsichritzis4daa1de2018-07-23 09:11:59 +010021 ********************************************************************/
Louis Mayencourt254f6f02019-04-09 14:11:06 +010022#define CLUSTERIDR_EL1 S3_0_C15_C3_1
23
John Tsichritzis4daa1de2018-07-23 09:11:59 +010024#define CLUSTERIDR_REV_SHIFT U(0)
25#define CLUSTERIDR_REV_BITS U(4)
26#define CLUSTERIDR_VAR_SHIFT U(4)
27#define CLUSTERIDR_VAR_BITS U(4)
Louis Mayencourt254f6f02019-04-09 14:11:06 +010028
29/********************************************************************
30 * DSU Cluster Auxiliary Control registers definitions
31 ********************************************************************/
32#define CLUSTERACTLR_EL1 S3_0_C15_C3_3
John Tsichritzis4daa1de2018-07-23 09:11:59 +010033
Louis Mayencourt4498b152019-04-09 16:29:01 +010034#define CLUSTERACTLR_EL1_DISABLE_CLOCK_GATING (ULL(1) << 15)
35
John Tsichritzis4daa1de2018-07-23 09:11:59 +010036/********************************************************************
Louis Mayencourt254f6f02019-04-09 14:11:06 +010037 * Masks applied for DSU errata workarounds
John Tsichritzis4daa1de2018-07-23 09:11:59 +010038 ********************************************************************/
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +000039#define DSU_ERRATA_936184_MASK (U(0x3) << 15)
John Tsichritzis4daa1de2018-07-23 09:11:59 +010040
41#endif /* DSU_DEF_H */