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Konstantin Porotchkin5d93d082018-04-24 19:23:09 +03001/*
2 * Copyright (C) 2018 Marvell International Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 * https://spdx.org/licenses
6 */
7
8/* Marvell CP110 SoC COMPHY unit driver */
9
10#ifndef _PHY_COMPHY_CP110_H
11#define _PHY_COMPHY_CP110_H
12
13#define SD_ADDR(base, lane) (base + 0x1000 * lane)
14#define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
15#define COMPHY_ADDR(base, lane) (base + 0x28 * lane)
16
17#define MAX_NUM_OF_FFE 8
18#define RX_TRAINING_TIMEOUT 500
19
20/* Comphy registers */
21#define COMMON_PHY_CFG1_REG 0x0
22#define COMMON_PHY_CFG1_PWR_UP_OFFSET 1
23#define COMMON_PHY_CFG1_PWR_UP_MASK \
24 (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET)
25#define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2
26#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \
27 (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET)
28#define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 13
29#define COMMON_PHY_CFG1_CORE_RSTN_MASK \
30 (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET)
31#define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 14
32#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \
33 (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET)
34#define COMMON_PHY_PHY_MODE_OFFSET 15
35#define COMMON_PHY_PHY_MODE_MASK \
36 (0x1 << COMMON_PHY_PHY_MODE_OFFSET)
37
38#define COMMON_PHY_CFG6_REG 0x14
39#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
40#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
41 (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
42
43#define COMMON_PHY_CFG6_REG 0x14
44#define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18
45#define COMMON_PHY_CFG6_IF_40_SEL_MASK \
46 (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET)
47
48#define COMMON_SELECTOR_PHY_REG_OFFSET 0x140
49#define COMMON_SELECTOR_PIPE_REG_OFFSET 0x144
50#define COMMON_SELECTOR_COMPHY_MASK 0xf
51#define COMMON_SELECTOR_COMPHYN_FIELD_WIDTH 4
52#define COMMON_SELECTOR_COMPHYN_SATA 0x4
53#define COMMON_SELECTOR_PIPE_COMPHY_PCIE 0x4
54#define COMMON_SELECTOR_PIPE_COMPHY_USBH 0x1
55#define COMMON_SELECTOR_PIPE_COMPHY_USBD 0x2
56
57/* SGMII/HS-SGMII/SFI/RXAUI */
58#define COMMON_SELECTOR_COMPHY0_1_2_NETWORK 0x1
59#define COMMON_SELECTOR_COMPHY3_RXAUI 0x1
60#define COMMON_SELECTOR_COMPHY3_SGMII 0x2
61#define COMMON_SELECTOR_COMPHY4_PORT1 0x1
62#define COMMON_SELECTOR_COMPHY4_ALL_OTHERS 0x2
63#define COMMON_SELECTOR_COMPHY5_RXAUI 0x2
64#define COMMON_SELECTOR_COMPHY5_SGMII 0x1
65
66#define COMMON_PHY_SD_CTRL1 0x148
67#define COMMON_PHY_SD_CTRL1_COMPHY_0_PORT_OFFSET 0
68#define COMMON_PHY_SD_CTRL1_COMPHY_1_PORT_OFFSET 4
69#define COMMON_PHY_SD_CTRL1_COMPHY_2_PORT_OFFSET 8
70#define COMMON_PHY_SD_CTRL1_COMPHY_3_PORT_OFFSET 12
71#define COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK 0xFFFF
72#define COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK 0xFF
73#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24
74#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \
75 (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET)
76#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25
77#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \
78 (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET)
79#define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26
80#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \
81 (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET)
82#define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27
83#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \
84 (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET)
85
86/* DFX register */
87#define DFX_BASE (0x400000)
88#define DFX_DEV_GEN_CTRL12_REG (0x280)
89#define DFX_DEV_GEN_PCIE_CLK_SRC_MUX (0x3)
90#define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7
91#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \
92 (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET)
93
94/* SerDes IP registers */
95#define SD_EXTERNAL_CONFIG0_REG 0
96#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1
97#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \
98 (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET)
99#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3
100#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \
101 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET)
102#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7
103#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \
104 (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET)
105#define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11
106#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \
107 (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET)
108#define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12
109#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \
110 (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET)
111#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14
112#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \
113 (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET)
114#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15
115#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \
116 (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET)
117
118#define SD_EXTERNAL_CONFIG1_REG 0x4
119#define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3
120#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \
121 (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET)
122#define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4
123#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \
124 (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET)
125#define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5
126#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \
127 (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET)
128#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6
129#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \
130 (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET)
131
132#define SD_EXTERNAL_CONFIG2_REG 0x8
133#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4
134#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \
135 (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET)
136#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7
137#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \
138 (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET)
139
140#define SD_EXTERNAL_STATUS_REG 0xc
141#define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7
142#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \
143 (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET)
144
145#define SD_EXTERNAL_STATUS0_REG 0x18
146#define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2
147#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \
148 (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET)
149#define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3
150#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \
151 (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET)
152#define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4
153#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \
154 (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET)
155
156#define SD_EXTERNAL_STATAUS1_REG 0x1c
157#define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_OFFSET 0
158#define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_MASK \
159 (1 << SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_OFFSET)
160#define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_OFFSET 1
161#define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_MASK \
162 (1 << SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_FAILED_OFFSET)
163
164/* HPIPE registers */
165#define HPIPE_PWR_PLL_REG 0x4
166#define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0
167#define HPIPE_PWR_PLL_REF_FREQ_MASK \
168 (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET)
169#define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5
170#define HPIPE_PWR_PLL_PHY_MODE_MASK \
171 (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET)
172
173#define HPIPE_CAL_REG1_REG 0xc
174#define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10
175#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \
176 (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET)
177#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15
178#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \
179 (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET)
180
181#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18
182#define HPIPE_SQUELCH_THRESH_IN_OFFSET 8
183#define HPIPE_SQUELCH_THRESH_IN_MASK \
184 (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET)
185#define HPIPE_SQUELCH_DETECTED_OFFSET 14
186#define HPIPE_SQUELCH_DETECTED_MASK \
187 (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET)
188
189#define HPIPE_DFE_REG0 0x1c
190#define HPIPE_DFE_RES_FORCE_OFFSET 15
191#define HPIPE_DFE_RES_FORCE_MASK \
192 (0x1 << HPIPE_DFE_RES_FORCE_OFFSET)
193
194#define HPIPE_DFE_F3_F5_REG 0x28
195#define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14
196#define HPIPE_DFE_F3_F5_DFE_EN_MASK \
197 (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET)
198#define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15
199#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
200 (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
201
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200202#define HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG 0x30
203#define HPIPE_ADAPTED_DFE_RES_OFFSET 13
204#define HPIPE_ADAPTED_DFE_RES_MASK \
205 (0x3 << HPIPE_ADAPTED_DFE_RES_OFFSET)
206
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300207#define HPIPE_G1_SET_0_REG 0x34
208#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
209#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
210 (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET)
211#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6
212#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \
213 (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET)
214#define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7
215#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \
216 (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET)
217#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11
218#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \
219 (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET)
220
221#define HPIPE_G1_SET_1_REG 0x38
222#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
223#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
224 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +0200225#define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3
226#define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK \
227 (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET)
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300228#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
229#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
230 (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
231#define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8
232#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \
233 (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET)
234#define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10
235#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \
236 (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET)
237#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11
238#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \
239 (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET)
240
241#define HPIPE_G2_SET_0_REG 0x3c
242#define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1
243#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \
244 (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET)
245#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6
246#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \
247 (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET)
248#define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7
249#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \
250 (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET)
251#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11
252#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \
253 (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET)
254
255#define HPIPE_G2_SET_1_REG 0x40
256#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
257#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
258 (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
Grzegorz Jaszczyka91ea622018-07-16 12:18:03 +0200259#define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3
260#define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK \
261 (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET)
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300262#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
263#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
264 (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
265#define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8
266#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \
267 (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET)
268#define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10
269#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \
270 (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET)
271#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11
272#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \
273 (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET)
274
275#define HPIPE_G3_SET_0_REG 0x44
276#define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1
277#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \
278 (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET)
279#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6
280#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \
281 (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET)
282#define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7
283#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \
284 (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET)
285#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11
286#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \
287 (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET)
288#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12
289#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \
290 (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET)
291#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15
292#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \
293 (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET)
294
295#define HPIPE_G3_SET_1_REG 0x48
296#define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0
297#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \
298 (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET)
299#define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3
300#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \
301 (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET)
302#define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6
303#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \
304 (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET)
305#define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8
306#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \
307 (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET)
308#define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10
309#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \
310 (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET)
311#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11
312#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \
313 (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET)
314#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13
315#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \
316 (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET)
317
318#define HPIPE_PHY_TEST_CONTROL_REG 0x54
319#define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4
320#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \
321 (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET)
322#define HPIPE_PHY_TEST_RESET_OFFSET 14
323#define HPIPE_PHY_TEST_RESET_MASK \
324 (0x1 << HPIPE_PHY_TEST_RESET_OFFSET)
325#define HPIPE_PHY_TEST_EN_OFFSET 15
326#define HPIPE_PHY_TEST_EN_MASK \
327 (0x1 << HPIPE_PHY_TEST_EN_OFFSET)
328
329#define HPIPE_PHY_TEST_DATA_REG 0x6c
330#define HPIPE_PHY_TEST_DATA_OFFSET 0
331#define HPIPE_PHY_TEST_DATA_MASK \
332 (0xffff << HPIPE_PHY_TEST_DATA_OFFSET)
333
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200334#define HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG 0x80
335
336#define HPIPE_PHY_TEST_OOB_0_REGISTER 0x84
337#define HPIPE_PHY_PT_OOB_EN_OFFSET 14
338#define HPIPE_PHY_PT_OOB_EN_MASK \
339 (0x1 << HPIPE_PHY_PT_OOB_EN_OFFSET)
340#define HPIPE_PHY_TEST_PT_TESTMODE_OFFSET 12
341#define HPIPE_PHY_TEST_PT_TESTMODE_MASK \
342 (0x3 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET)
343
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300344#define HPIPE_LOOPBACK_REG 0x8c
345#define HPIPE_LOOPBACK_SEL_OFFSET 1
346#define HPIPE_LOOPBACK_SEL_MASK \
347 (0x7 << HPIPE_LOOPBACK_SEL_OFFSET)
348#define HPIPE_CDR_LOCK_OFFSET 7
349#define HPIPE_CDR_LOCK_MASK \
350 (0x1 << HPIPE_CDR_LOCK_OFFSET)
351#define HPIPE_CDR_LOCK_DET_EN_OFFSET 8
352#define HPIPE_CDR_LOCK_DET_EN_MASK \
353 (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET)
354
355#define HPIPE_INTERFACE_REG 0x94
356#define HPIPE_INTERFACE_GEN_MAX_OFFSET 10
357#define HPIPE_INTERFACE_GEN_MAX_MASK \
358 (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET)
359#define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12
360#define HPIPE_INTERFACE_DET_BYPASS_MASK \
361 (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET)
362#define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14
363#define HPIPE_INTERFACE_LINK_TRAIN_MASK \
364 (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET)
365
366#define HPIPE_G1_SET_2_REG 0xf4
367#define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0
368#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \
369 (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET)
370#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4
371#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \
372 (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET)
373
374#define HPIPE_G2_SET_2_REG 0xf8
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200375#define HPIPE_G2_SET_2_G2_TX_EMPH0_OFFSET 0
376#define HPIPE_G2_SET_2_G2_TX_EMPH0_MASK \
377 (0xf << HPIPE_G2_SET_2_G2_TX_EMPH0_OFFSET)
378#define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET 4
379#define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_MASK \
380 (0x1 << HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET)
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300381#define HPIPE_G2_TX_SSC_AMP_OFFSET 9
382#define HPIPE_G2_TX_SSC_AMP_MASK \
383 (0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET)
384
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200385#define HPIPE_G3_SET_2_REG 0xfc
386#define HPIPE_G3_SET_2_G3_TX_EMPH0_OFFSET 0
387#define HPIPE_G3_SET_2_G3_TX_EMPH0_MASK \
388 (0xf << HPIPE_G3_SET_2_G3_TX_EMPH0_OFFSET)
389#define HPIPE_G3_SET_2_G3_TX_EMPH0_EN_OFFSET 4
390#define HPIPE_G3_SET_2_G3_TX_EMPH0_EN_MASK \
391 (0x1 << HPIPE_G3_SET_2_G3_TX_EMPH0_EN_OFFSET)
392#define HPIPE_G3_TX_SSC_AMP_OFFSET 9
393#define HPIPE_G3_TX_SSC_AMP_MASK \
394 (0x7f << HPIPE_G3_TX_SSC_AMP_OFFSET)
395
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300396#define HPIPE_VDD_CAL_0_REG 0x108
397#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
398#define HPIPE_CAL_VDD_CONT_MODE_MASK \
399 (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET)
400
401#define HPIPE_VDD_CAL_CTRL_REG 0x114
402#define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5
403#define HPIPE_EXT_SELLV_RXSAMPL_MASK \
404 (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET)
405
406#define HPIPE_PCIE_REG0 0x120
407#define HPIPE_PCIE_IDLE_SYNC_OFFSET 12
408#define HPIPE_PCIE_IDLE_SYNC_MASK \
409 (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET)
410#define HPIPE_PCIE_SEL_BITS_OFFSET 13
411#define HPIPE_PCIE_SEL_BITS_MASK \
412 (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET)
413
414#define HPIPE_LANE_ALIGN_REG 0x124
415#define HPIPE_LANE_ALIGN_OFF_OFFSET 12
416#define HPIPE_LANE_ALIGN_OFF_MASK \
417 (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET)
418
419#define HPIPE_MISC_REG 0x13C
420#define HPIPE_MISC_CLK100M_125M_OFFSET 4
421#define HPIPE_MISC_CLK100M_125M_MASK \
422 (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET)
423#define HPIPE_MISC_ICP_FORCE_OFFSET 5
424#define HPIPE_MISC_ICP_FORCE_MASK \
425 (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET)
426#define HPIPE_MISC_TXDCLK_2X_OFFSET 6
427#define HPIPE_MISC_TXDCLK_2X_MASK \
428 (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET)
429#define HPIPE_MISC_CLK500_EN_OFFSET 7
430#define HPIPE_MISC_CLK500_EN_MASK \
431 (0x1 << HPIPE_MISC_CLK500_EN_OFFSET)
432#define HPIPE_MISC_REFCLK_SEL_OFFSET 10
433#define HPIPE_MISC_REFCLK_SEL_MASK \
434 (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET)
435
436#define HPIPE_RX_CONTROL_1_REG 0x140
437#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11
438#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \
439 (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET)
440#define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12
441#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \
442 (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET)
443
444#define HPIPE_PWR_CTR_REG 0x148
445#define HPIPE_PWR_CTR_RST_DFE_OFFSET 0
446#define HPIPE_PWR_CTR_RST_DFE_MASK \
447 (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET)
448#define HPIPE_PWR_CTR_SFT_RST_OFFSET 10
449#define HPIPE_PWR_CTR_SFT_RST_MASK \
450 (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET)
451
452#define HPIPE_SPD_DIV_FORCE_REG 0x154
453#define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7
454#define HPIPE_TXDIGCK_DIV_FORCE_MASK \
455 (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET)
456#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8
457#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \
458 (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET)
459#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10
460#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \
461 (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET)
462#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13
463#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \
464 (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET)
465#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15
466#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
467 (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
468
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200469/* HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIBRATION_CTRL_REG */
470#define HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG 0x168
471#define HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET 15
472#define HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK \
473 (0x1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET)
474#define HPIPE_CAL_OS_PH_EXT_OFFSET 8
475#define HPIPE_CAL_OS_PH_EXT_MASK \
476 (0x7f << HPIPE_CAL_OS_PH_EXT_OFFSET)
477
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300478#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
479#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
480#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
481 (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET)
482#define HPIPE_SMAPLER_OFFSET 12
483#define HPIPE_SMAPLER_MASK \
484 (0x1 << HPIPE_SMAPLER_OFFSET)
485
486#define HPIPE_TX_REG1_REG 0x174
487#define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5
488#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \
489 (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET)
490#define HPIPE_TX_REG1_SLC_EN_OFFSET 10
491#define HPIPE_TX_REG1_SLC_EN_MASK \
492 (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET)
493
494#define HPIPE_PWR_CTR_DTL_REG 0x184
495#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0
496#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \
497 (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET)
498#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1
499#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \
500 (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET)
501#define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2
502#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \
503 (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET)
504#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4
505#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \
506 (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET)
507#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10
508#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \
509 (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET)
510#define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12
511#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \
512 (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET)
513#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14
514#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \
515 (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET)
516
517#define HPIPE_PHASE_CONTROL_REG 0x188
518#define HPIPE_OS_PH_OFFSET_OFFSET 0
519#define HPIPE_OS_PH_OFFSET_MASK \
520 (0x7f << HPIPE_OS_PH_OFFSET_OFFSET)
521#define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7
522#define HPIPE_OS_PH_OFFSET_FORCE_MASK \
523 (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET)
524#define HPIPE_OS_PH_VALID_OFFSET 8
525#define HPIPE_OS_PH_VALID_MASK \
526 (0x1 << HPIPE_OS_PH_VALID_OFFSET)
527
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200528#define HPIPE_DATA_PHASE_OFF_CTRL_REG 0x1A0
529#define HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET 9
530#define HPIPE_DATA_PHASE_ADAPTED_OS_PH_MASK \
531 (0x7f << HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET)
532
533#define HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG 0x1A4
534#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET 12
535#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_MASK \
536 (0x3 << HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET)
537#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET 8
538#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_MASK \
539 (0xf << HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET)
540
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300541#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8
542#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0
543#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \
544 (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET)
545#define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4
546#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \
547 (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET)
548#define HPIPE_SQ_DEGLITCH_EN_OFFSET 8
549#define HPIPE_SQ_DEGLITCH_EN_MASK \
550 (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET)
551
552#define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214
553#define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7
554#define HPIPE_TRAIN_PAT_NUM_MASK \
555 (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET)
556
557#define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220
558#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12
559#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \
560 (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET)
561
562#define HPIPE_DME_REG 0x228
563#define HPIPE_DME_ETHERNET_MODE_OFFSET 7
564#define HPIPE_DME_ETHERNET_MODE_MASK \
565 (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
566
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200567#define HPIPE_TRX_TRAIN_CTRL_0_REG 0x22c
568#define HPIPE_TRX_TX_F0T_EO_BASED_OFFSET 14
569#define HPIPE_TRX_TX_F0T_EO_BASED_MASK \
570 (1 << HPIPE_TRX_TX_F0T_EO_BASED_OFFSET)
571#define HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET 6
572#define HPIPE_TRX_UPDATE_THEN_HOLD_MASK \
573 (1 << HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET)
574#define HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET 5
575#define HPIPE_TRX_TX_CTRL_CLK_EN_MASK \
576 (1 << HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET)
577#define HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET 4
578#define HPIPE_TRX_RX_ANA_IF_CLK_ENE_MASK \
579 (1 << HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET)
580#define HPIPE_TRX_TX_TRAIN_EN_OFFSET 1
581#define HPIPE_TRX_TX_TRAIN_EN_MASK \
582 (1 << HPIPE_TRX_TX_TRAIN_EN_OFFSET)
583#define HPIPE_TRX_RX_TRAIN_EN_OFFSET 0
584#define HPIPE_TRX_RX_TRAIN_EN_MASK \
585 (1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET)
586
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300587#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
588#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
589#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
590 (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET)
591
592#define HPIPE_TX_TRAIN_CTRL_REG 0x26C
593#define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0
594#define HPIPE_TX_TRAIN_CTRL_G1_MASK \
595 (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET)
596#define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1
597#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \
598 (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET)
599#define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2
600#define HPIPE_TX_TRAIN_CTRL_G0_MASK \
601 (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET)
602
603#define HPIPE_TX_TRAIN_CTRL_4_REG 0x278
604#define HPIPE_TRX_TRAIN_TIMER_OFFSET 0
605#define HPIPE_TRX_TRAIN_TIMER_MASK \
606 (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET)
607
608#define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4
609#define HPIPE_RX_TRAIN_TIMER_OFFSET 0
610#define HPIPE_RX_TRAIN_TIMER_MASK \
611 (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET)
612#define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11
613#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \
614 (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET)
615#define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12
616#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \
617 (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET)
618#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13
619#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \
620 (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET)
621#define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14
622#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
623 (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
624
Grzegorz Jaszczyk2ed16f52018-06-29 18:00:33 +0200625#define HPIPE_INTERRUPT_1_REGISTER 0x2AC
626#define HPIPE_TRX_TRAIN_FAILED_OFFSET 6
627#define HPIPE_TRX_TRAIN_FAILED_MASK \
628 (1 << HPIPE_TRX_TRAIN_FAILED_OFFSET)
629#define HPIPE_TRX_TRAIN_TIME_OUT_INT_OFFSET 5
630#define HPIPE_TRX_TRAIN_TIME_OUT_INT_MASK \
631 (1 << HPIPE_TRX_TRAIN_TIME_OUT_INT_OFFSET)
632#define HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET 4
633#define HPIPE_INTERRUPT_TRX_TRAIN_DONE_MASK \
634 (1 << HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET)
635#define HPIPE_INTERRUPT_DFE_DONE_INT_OFFSET 3
636#define HPIPE_INTERRUPT_DFE_DONE_INT_MASK \
637 (1 << HPIPE_INTERRUPT_DFE_DONE_INT_OFFSET)
638#define HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_OFFSET 1
639#define HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_MASK \
640 (1 << HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_OFFSET)
641
Konstantin Porotchkin5d93d082018-04-24 19:23:09 +0300642#define HPIPE_TX_TRAIN_REG 0x31C
643#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
644#define HPIPE_TX_TRAIN_CHK_INIT_MASK \
645 (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET)
646#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7
647#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \
648 (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET)
649#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8
650#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \
651 (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET)
652#define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9
653#define HPIPE_TX_TRAIN_PAT_SEL_MASK \
654 (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET)
655
656#define HPIPE_SAVED_DFE_VALUES_REG 0x328
657#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10
658#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \
659 (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET)
660
661#define HPIPE_CDR_CONTROL_REG 0x418
662#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14
663#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \
664 (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET)
665#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12
666#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \
667 (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET)
668#define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9
669#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \
670 (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET)
671#define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6
672#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \
673 (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET)
674
675#define HPIPE_TX_TRAIN_CTRL_11_REG 0x438
676#define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6
677#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \
678 (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET)
679#define HPIPE_TX_NUM_OF_PRESET_OFFSET 10
680#define HPIPE_TX_NUM_OF_PRESET_MASK \
681 (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET)
682#define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15
683#define HPIPE_TX_SWEEP_PRESET_EN_MASK \
684 (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET)
685
686#define HPIPE_G1_SETTINGS_3_REG 0x440
687#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0
688#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \
689 (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET)
690#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4
691#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \
692 (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET)
693#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7
694#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \
695 (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET)
696#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9
697#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \
698 (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET)
699#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12
700#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \
701 (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET)
702#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14
703#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \
704 (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET)
705
706#define HPIPE_G1_SETTINGS_4_REG 0x444
707#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8
708#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \
709 (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET)
710
711#define HPIPE_G2_SETTINGS_4_REG 0x44c
712#define HPIPE_G2_DFE_RES_OFFSET 8
713#define HPIPE_G2_DFE_RES_MASK \
714 (0x3 << HPIPE_G2_DFE_RES_OFFSET)
715
716#define HPIPE_G3_SETTING_3_REG 0x450
717#define HPIPE_G3_FFE_CAP_SEL_OFFSET 0
718#define HPIPE_G3_FFE_CAP_SEL_MASK \
719 (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET)
720#define HPIPE_G3_FFE_RES_SEL_OFFSET 4
721#define HPIPE_G3_FFE_RES_SEL_MASK \
722 (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET)
723#define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7
724#define HPIPE_G3_FFE_SETTING_FORCE_MASK \
725 (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET)
726#define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12
727#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \
728 (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET)
729#define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14
730#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \
731 (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET)
732
733#define HPIPE_G3_SETTING_4_REG 0x454
734#define HPIPE_G3_DFE_RES_OFFSET 8
735#define HPIPE_G3_DFE_RES_MASK (0x3 << HPIPE_G3_DFE_RES_OFFSET)
736
737#define HPIPE_TX_PRESET_INDEX_REG 0x468
738#define HPIPE_TX_PRESET_INDEX_OFFSET 0
739#define HPIPE_TX_PRESET_INDEX_MASK \
740 (0xf << HPIPE_TX_PRESET_INDEX_OFFSET)
741
742#define HPIPE_DFE_CONTROL_REG 0x470
743#define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14
744#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \
745 (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET)
746
747#define HPIPE_DFE_CTRL_28_REG 0x49C
748#define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7
749#define HPIPE_DFE_CTRL_28_PIPE4_MASK \
750 (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET)
751
752#define HPIPE_G1_SETTING_5_REG 0x538
753#define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0
754#define HPIPE_G1_SETTING_5_G1_ICP_MASK \
755 (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET)
756
757#define HPIPE_G3_SETTING_5_REG 0x548
758#define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0
759#define HPIPE_G3_SETTING_5_G3_ICP_MASK \
760 (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET)
761
762#define HPIPE_LANE_CONFIG0_REG 0x600
763#define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0
764#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \
765 (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET)
766
767#define HPIPE_LANE_STATUS1_REG 0x60C
768#define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0
769#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \
770 (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET)
771
772#define HPIPE_LANE_CFG4_REG 0x620
773#define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0
774#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \
775 (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET)
776#define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3
777#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \
778 (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET)
779#define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6
780#define HPIPE_LANE_CFG4_DFE_OVER_MASK \
781 (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET)
782#define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7
783#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \
784 (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET)
785
786#define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8
787#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0
788#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \
789 (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET)
790#define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1
791#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \
792 (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET)
793#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2
794#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \
795 (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET)
796
797#define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C
798#define HPIPE_CFG_PHY_RC_EP_OFFSET 12
799#define HPIPE_CFG_PHY_RC_EP_MASK \
800 (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET)
801
802#define HPIPE_LANE_EQ_CFG1_REG 0x6a0
803#define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12
804#define HPIPE_CFG_UPDATE_POLARITY_MASK \
805 (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET)
806
807#define HPIPE_LANE_EQ_CFG2_REG 0x6a4
808#define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET 14
809#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK \
810 (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET)
811
812#define HPIPE_RST_CLK_CTRL_REG 0x704
813#define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0
814#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \
815 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET)
816#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2
817#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \
818 (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET)
819#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3
820#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \
821 (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET)
822#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9
823#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \
824 (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET)
825
826#define HPIPE_TST_MODE_CTRL_REG 0x708
827#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2
828#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \
829 (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET)
830
831#define HPIPE_CLK_SRC_LO_REG 0x70c
832#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1
833#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \
834 (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET)
835#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2
836#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \
837 (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET)
838#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5
839#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \
840 (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET)
841
842#define HPIPE_CLK_SRC_HI_REG 0x710
843#define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0
844#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \
845 (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET)
846#define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1
847#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \
848 (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET)
849#define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2
850#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \
851 (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET)
852#define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7
853#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \
854 (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET)
855
856#define HPIPE_GLOBAL_MISC_CTRL 0x718
857#define HPIPE_GLOBAL_PM_CTRL 0x740
858#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0
859#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \
860 (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET)
861
862/* General defines */
863#define PLL_LOCK_TIMEOUT 15000
864
865#endif /* _PHY_COMPHY_CP110_H */
866