mvebu: cp110: introduce COMPHY porting layer
Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.
Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h
If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".
The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h
index 6afa2c2..1d7aec8 100644
--- a/drivers/marvell/comphy/comphy-cp110.h
+++ b/drivers/marvell/comphy/comphy-cp110.h
@@ -199,6 +199,11 @@
#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \
(0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET)
+#define HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG 0x30
+#define HPIPE_ADAPTED_DFE_RES_OFFSET 13
+#define HPIPE_ADAPTED_DFE_RES_MASK \
+ (0x3 << HPIPE_ADAPTED_DFE_RES_OFFSET)
+
#define HPIPE_G1_SET_0_REG 0x34
#define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1
#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \
@@ -326,6 +331,16 @@
#define HPIPE_PHY_TEST_DATA_MASK \
(0xffff << HPIPE_PHY_TEST_DATA_OFFSET)
+#define HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG 0x80
+
+#define HPIPE_PHY_TEST_OOB_0_REGISTER 0x84
+#define HPIPE_PHY_PT_OOB_EN_OFFSET 14
+#define HPIPE_PHY_PT_OOB_EN_MASK \
+ (0x1 << HPIPE_PHY_PT_OOB_EN_OFFSET)
+#define HPIPE_PHY_TEST_PT_TESTMODE_OFFSET 12
+#define HPIPE_PHY_TEST_PT_TESTMODE_MASK \
+ (0x3 << HPIPE_PHY_TEST_PT_TESTMODE_OFFSET)
+
#define HPIPE_LOOPBACK_REG 0x8c
#define HPIPE_LOOPBACK_SEL_OFFSET 1
#define HPIPE_LOOPBACK_SEL_MASK \
@@ -357,10 +372,27 @@
(0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET)
#define HPIPE_G2_SET_2_REG 0xf8
+#define HPIPE_G2_SET_2_G2_TX_EMPH0_OFFSET 0
+#define HPIPE_G2_SET_2_G2_TX_EMPH0_MASK \
+ (0xf << HPIPE_G2_SET_2_G2_TX_EMPH0_OFFSET)
+#define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET 4
+#define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_MASK \
+ (0x1 << HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET)
#define HPIPE_G2_TX_SSC_AMP_OFFSET 9
#define HPIPE_G2_TX_SSC_AMP_MASK \
(0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET)
+#define HPIPE_G3_SET_2_REG 0xfc
+#define HPIPE_G3_SET_2_G3_TX_EMPH0_OFFSET 0
+#define HPIPE_G3_SET_2_G3_TX_EMPH0_MASK \
+ (0xf << HPIPE_G3_SET_2_G3_TX_EMPH0_OFFSET)
+#define HPIPE_G3_SET_2_G3_TX_EMPH0_EN_OFFSET 4
+#define HPIPE_G3_SET_2_G3_TX_EMPH0_EN_MASK \
+ (0x1 << HPIPE_G3_SET_2_G3_TX_EMPH0_EN_OFFSET)
+#define HPIPE_G3_TX_SSC_AMP_OFFSET 9
+#define HPIPE_G3_TX_SSC_AMP_MASK \
+ (0x7f << HPIPE_G3_TX_SSC_AMP_OFFSET)
+
#define HPIPE_VDD_CAL_0_REG 0x108
#define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15
#define HPIPE_CAL_VDD_CONT_MODE_MASK \
@@ -434,6 +466,15 @@
#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \
(0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET)
+/* HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIBRATION_CTRL_REG */
+#define HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG 0x168
+#define HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET 15
+#define HPIPE_CAL_RXCLKALIGN_90_EXT_EN_MASK \
+ (0x1 << HPIPE_CAL_RXCLKALIGN_90_EXT_EN_OFFSET)
+#define HPIPE_CAL_OS_PH_EXT_OFFSET 8
+#define HPIPE_CAL_OS_PH_EXT_MASK \
+ (0x7f << HPIPE_CAL_OS_PH_EXT_OFFSET)
+
#define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C
#define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6
#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \
@@ -484,6 +525,19 @@
#define HPIPE_OS_PH_VALID_MASK \
(0x1 << HPIPE_OS_PH_VALID_OFFSET)
+#define HPIPE_DATA_PHASE_OFF_CTRL_REG 0x1A0
+#define HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET 9
+#define HPIPE_DATA_PHASE_ADAPTED_OS_PH_MASK \
+ (0x7f << HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET)
+
+#define HPIPE_ADAPTED_FFE_CAPACITOR_COUNTER_CTRL_REG 0x1A4
+#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET 12
+#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_MASK \
+ (0x3 << HPIPE_ADAPTED_FFE_ADAPTED_FFE_RES_OFFSET)
+#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET 8
+#define HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_MASK \
+ (0xf << HPIPE_ADAPTED_FFE_ADAPTED_FFE_CAP_OFFSET)
+
#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8
#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0
#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \
@@ -510,6 +564,26 @@
#define HPIPE_DME_ETHERNET_MODE_MASK \
(0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET)
+#define HPIPE_TRX_TRAIN_CTRL_0_REG 0x22c
+#define HPIPE_TRX_TX_F0T_EO_BASED_OFFSET 14
+#define HPIPE_TRX_TX_F0T_EO_BASED_MASK \
+ (1 << HPIPE_TRX_TX_F0T_EO_BASED_OFFSET)
+#define HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET 6
+#define HPIPE_TRX_UPDATE_THEN_HOLD_MASK \
+ (1 << HPIPE_TRX_UPDATE_THEN_HOLD_OFFSET)
+#define HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET 5
+#define HPIPE_TRX_TX_CTRL_CLK_EN_MASK \
+ (1 << HPIPE_TRX_TX_CTRL_CLK_EN_OFFSET)
+#define HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET 4
+#define HPIPE_TRX_RX_ANA_IF_CLK_ENE_MASK \
+ (1 << HPIPE_TRX_RX_ANA_IF_CLK_ENE_OFFSET)
+#define HPIPE_TRX_TX_TRAIN_EN_OFFSET 1
+#define HPIPE_TRX_TX_TRAIN_EN_MASK \
+ (1 << HPIPE_TRX_TX_TRAIN_EN_OFFSET)
+#define HPIPE_TRX_RX_TRAIN_EN_OFFSET 0
+#define HPIPE_TRX_RX_TRAIN_EN_MASK \
+ (1 << HPIPE_TRX_RX_TRAIN_EN_OFFSET)
+
#define HPIPE_TX_TRAIN_CTRL_0_REG 0x268
#define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15
#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \
@@ -548,6 +622,23 @@
#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \
(0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET)
+#define HPIPE_INTERRUPT_1_REGISTER 0x2AC
+#define HPIPE_TRX_TRAIN_FAILED_OFFSET 6
+#define HPIPE_TRX_TRAIN_FAILED_MASK \
+ (1 << HPIPE_TRX_TRAIN_FAILED_OFFSET)
+#define HPIPE_TRX_TRAIN_TIME_OUT_INT_OFFSET 5
+#define HPIPE_TRX_TRAIN_TIME_OUT_INT_MASK \
+ (1 << HPIPE_TRX_TRAIN_TIME_OUT_INT_OFFSET)
+#define HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET 4
+#define HPIPE_INTERRUPT_TRX_TRAIN_DONE_MASK \
+ (1 << HPIPE_INTERRUPT_TRX_TRAIN_DONE_OFFSET)
+#define HPIPE_INTERRUPT_DFE_DONE_INT_OFFSET 3
+#define HPIPE_INTERRUPT_DFE_DONE_INT_MASK \
+ (1 << HPIPE_INTERRUPT_DFE_DONE_INT_OFFSET)
+#define HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_OFFSET 1
+#define HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_MASK \
+ (1 << HPIPE_INTERRUPT_RX_TRAIN_COMPLETE_INT_OFFSET)
+
#define HPIPE_TX_TRAIN_REG 0x31C
#define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4
#define HPIPE_TX_TRAIN_CHK_INIT_MASK \