mvebu: cp110: fix spelling in register definition
Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).
Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h
index 925abb5..6afa2c2 100644
--- a/drivers/marvell/comphy/comphy-cp110.h
+++ b/drivers/marvell/comphy/comphy-cp110.h
@@ -217,9 +217,9 @@
#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3
-#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET)
+#define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3
+#define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK \
+ (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
@@ -251,9 +251,9 @@
#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3
-#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \
- (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET)
+#define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3
+#define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK \
+ (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)