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git01.mediatek.com / filogic / atf / 2e86cb10667472375a39c345bfa19371a83f61c7 / . / include / plat / arm / common / aarch64 / arm_macros.S
blob: 384bb5140c7b1406f671519b3c6277b53631a7cd [file] [log] [blame]
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]1/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30#ifndef __ARM_MACROS_S__
31#define __ARM_MACROS_S__
32
33#include <cci.h>
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]34#include <gic_common.h>
35#include <gicv2.h>
36#include <gicv3.h>
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]37#include <platform_def.h>
38
39.section .rodata.gic_reg_name, "aS"
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]40/* Applicable only to GICv2 and GICv3 with SRE disabled (legacy mode) */
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]41gicc_regs:
42 .asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]43
44/* Applicable only to GICv3 with SRE enabled */
45icc_regs:
46 .asciz "icc_hppir0_el1", "icc_hppir1_el1", "icc_ctlr_el3", ""
47
48/* Registers common to both GICv2 and GICv3 */
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]49gicd_pend_reg:
50 .asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
51 " Offset:\t\t\tvalue\n"
52newline:
53 .asciz "\n"
54spacer:
55 .asciz ":\t\t0x"
56
57 /* ---------------------------------------------
58 * The below utility macro prints out relevant GIC
59 * registers whenever an unhandled exception is
Juan Castillo7d199412015-12-14 09:35:25 +0000[diff] [blame]60 * taken in BL31 on ARM standard platforms.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]61 * Expects: GICD base in x16, GICC base in x17
62 * Clobbers: x0 - x10, sp
63 * ---------------------------------------------
64 */
65 .macro arm_print_gic_regs
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]66 /* Check for GICv3 system register access */
67 mrs x7, id_aa64pfr0_el1
68 ubfx x7, x7, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_WIDTH
69 cmp x7, #1
70 b.ne print_gicv2
71
72 /* Check for SRE enable */
73 mrs x8, ICC_SRE_EL3
74 tst x8, #ICC_SRE_SRE_BIT
75 b.eq print_gicv2
76
77 /* Load the icc reg list to x6 */
78 adr x6, icc_regs
79 /* Load the icc regs to gp regs used by str_in_crash_buf_print */
80 mrs x8, ICC_HPPIR0_EL1
81 mrs x9, ICC_HPPIR1_EL1
82 mrs x10, ICC_CTLR_EL3
83 /* Store to the crash buf and print to console */
84 bl str_in_crash_buf_print
85 b print_gic_common
86
87print_gicv2:
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]88 /* Load the gicc reg list to x6 */
89 adr x6, gicc_regs
90 /* Load the gicc regs to gp regs used by str_in_crash_buf_print */
91 ldr w8, [x17, #GICC_HPPIR]
92 ldr w9, [x17, #GICC_AHPPIR]
93 ldr w10, [x17, #GICC_CTLR]
94 /* Store to the crash buf and print to console */
95 bl str_in_crash_buf_print
96
Soby Mathew12012dd2015-10-26 14:01:53 +0000[diff] [blame]97print_gic_common:
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]98 /* Print the GICD_ISPENDR regs */
99 add x7, x16, #GICD_ISPENDR
100 adr x4, gicd_pend_reg
101 bl asm_print_str
102gicd_ispendr_loop:
103 sub x4, x7, x16
104 cmp x4, #0x280
105 b.eq exit_print_gic_regs
106 bl asm_print_hex
107
108 adr x4, spacer
109 bl asm_print_str
110
111 ldr x4, [x7], #8
112 bl asm_print_hex
113
114 adr x4, newline
115 bl asm_print_str
116 b gicd_ispendr_loop
117exit_print_gic_regs:
118 .endm
119
120
121.section .rodata.cci_reg_name, "aS"
122cci_iface_regs:
123 .asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
124
125 /* ------------------------------------------------
126 * The below required platform porting macro prints
127 * out relevant interconnect registers whenever an
Juan Castillo7d199412015-12-14 09:35:25 +0000[diff] [blame]128 * unhandled exception is taken in BL31.
Dan Handley9df48042015-03-19 18:58:55 +0000[diff] [blame]129 * Clobbers: x0 - x9, sp
130 * ------------------------------------------------
131 */
132 .macro plat_print_interconnect_regs
133 adr x6, cci_iface_regs
134 /* Store in x7 the base address of the first interface */
135 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
136 PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX))
137 ldr w8, [x7, #SNOOP_CTRL_REG]
138 /* Store in x7 the base address of the second interface */
139 mov_imm x7, (PLAT_ARM_CCI_BASE + SLAVE_IFACE_OFFSET( \
140 PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX))
141 ldr w9, [x7, #SNOOP_CTRL_REG]
142 /* Store to the crash buf and print to console */
143 bl str_in_crash_buf_print
144 .endm
145
146
147#endif /* __ARM_MACROS_S__ */