Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 1 | /* |
Bipin Ravi | e0b52cc | 2023-01-18 11:03:21 -0600 | [diff] [blame] | 2 | * Copyright (c) 2021-2023, Arm Limited. All rights reserved. |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
| 9 | #include <common/bl_common.h> |
| 10 | #include <cortex_a78c.h> |
| 11 | #include <cpu_macros.S> |
| 12 | #include <plat_macros.S> |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 13 | #include "wa_cve_2022_23960_bhb_vector.S" |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 14 | |
| 15 | /* Hardware handled coherency */ |
| 16 | #if HW_ASSISTED_COHERENCY == 0 |
| 17 | #error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 18 | #endif |
| 19 | |
Akram Ahmad | dbff7cf | 2022-07-19 14:38:46 +0100 | [diff] [blame] | 20 | /* -------------------------------------------------- |
Bipin Ravi | bf205fc | 2023-03-14 10:04:23 -0500 | [diff] [blame] | 21 | * Errata Workaround for A78C Erratum 1827430. |
| 22 | * This applies to revision r0p0 of the Cortex A78C |
| 23 | * processor and is fixed in r0p1. |
| 24 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 25 | * Shall clobber: x0-x17 |
| 26 | * -------------------------------------------------- |
| 27 | */ |
| 28 | func errata_a78c_1827430_wa |
| 29 | mov x17, x30 |
| 30 | bl check_errata_1827430 |
| 31 | cbz x0, 1f |
| 32 | |
| 33 | /* Disable allocation of splintered pages in the L2 TLB */ |
| 34 | mrs x1, CORTEX_A78C_CPUECTLR_EL1 |
| 35 | orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN |
| 36 | msr CORTEX_A78C_CPUECTLR_EL1, x1 |
| 37 | 1: |
| 38 | ret x17 |
| 39 | endfunc errata_a78c_1827430_wa |
| 40 | |
| 41 | func check_errata_1827430 |
| 42 | /* Applies to revision r0p0 only */ |
| 43 | mov x1, #0x00 |
| 44 | b cpu_rev_var_ls |
| 45 | endfunc check_errata_1827430 |
| 46 | |
| 47 | /* -------------------------------------------------- |
Bipin Ravi | e49c704 | 2023-03-14 11:03:24 -0500 | [diff] [blame] | 48 | * Errata Workaround for A78C Erratum 1827440. |
| 49 | * This applies to revision r0p0 of the Cortex A78C |
| 50 | * processor and is fixed in r0p1. |
| 51 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 52 | * Shall clobber: x0-x17 |
| 53 | * -------------------------------------------------- |
| 54 | */ |
| 55 | func errata_a78c_1827440_wa |
| 56 | mov x17, x30 |
| 57 | bl check_errata_1827440 |
| 58 | cbz x0, 1f |
| 59 | |
| 60 | /* Force Atomic Store to WB memory be done in L1 data cache */ |
| 61 | mrs x1, CORTEX_A78C_CPUACTLR2_EL1 |
| 62 | orr x1, x1, #BIT(2) |
| 63 | msr CORTEX_A78C_CPUACTLR2_EL1, x1 |
| 64 | 1: |
| 65 | ret x17 |
| 66 | endfunc errata_a78c_1827440_wa |
| 67 | |
| 68 | func check_errata_1827440 |
| 69 | /* Applies to revision r0p0 only */ |
| 70 | mov x1, #0x00 |
| 71 | b cpu_rev_var_ls |
| 72 | endfunc check_errata_1827440 |
| 73 | |
| 74 | /* -------------------------------------------------- |
Akram Ahmad | fbc1edb | 2022-09-06 11:23:25 +0100 | [diff] [blame] | 75 | * Errata Workaround for Cortex A78C Erratum 2376749. |
| 76 | * This applies to revision r0p1 and r0p2 of the A78C |
| 77 | * and is currently open. It is a Cat B erratum. |
| 78 | * Inputs: |
| 79 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 80 | * Shall clobber: x0-x4, x17 |
| 81 | * -------------------------------------------------- |
| 82 | */ |
| 83 | func errata_a78c_2376749_wa |
| 84 | /* Check revision */ |
| 85 | mov x17, x30 |
| 86 | bl check_errata_2376749 |
| 87 | cbz x0, 1f |
| 88 | /* Set CPUACTLR2_EL1[0] to 1. */ |
| 89 | mrs x1, CORTEX_A78C_CPUACTLR2_EL1 |
| 90 | orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0 |
| 91 | msr CORTEX_A78C_CPUACTLR2_EL1, x1 |
| 92 | 1: |
| 93 | ret x17 |
| 94 | endfunc errata_a78c_2376749_wa |
| 95 | |
| 96 | func check_errata_2376749 |
| 97 | /* Applies to r0p1 and r0p2*/ |
| 98 | mov x1, #0x01 |
| 99 | mov x2, #0x02 |
| 100 | b cpu_rev_var_range |
| 101 | endfunc check_errata_2376749 |
| 102 | |
| 103 | /* -------------------------------------------------- |
Akram Ahmad | dbff7cf | 2022-07-19 14:38:46 +0100 | [diff] [blame] | 104 | * Errata Workaround for Cortex A78C Erratum 2395411. |
| 105 | * This applies to revision r0p1 and r0p2 of the A78C |
| 106 | * and is currently open. It is a Cat B erratum. |
| 107 | * Inputs: |
| 108 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 109 | * Shall clobber: x0-x4, x17 |
| 110 | * -------------------------------------------------- |
| 111 | */ |
| 112 | func errata_a78c_2395411_wa |
| 113 | /* Check revision. */ |
| 114 | mov x17, x30 |
| 115 | bl check_errata_2395411 |
| 116 | cbz x0, 1f |
| 117 | |
| 118 | /* Set CPUACTRL2_EL1[40] to 1. */ |
| 119 | mrs x1, CORTEX_A78C_CPUACTLR2_EL1 |
| 120 | orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40 |
| 121 | msr CORTEX_A78C_CPUACTLR2_EL1, x1 |
| 122 | 1: |
| 123 | ret x17 |
| 124 | endfunc errata_a78c_2395411_wa |
| 125 | |
| 126 | func check_errata_2395411 |
| 127 | /* Applies to r0p1 and r0p2 */ |
| 128 | mov x1, #0x01 |
| 129 | mov x2, #0x02 |
| 130 | b cpu_rev_var_range |
| 131 | endfunc check_errata_2395411 |
| 132 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 133 | #if WORKAROUND_CVE_2022_23960 |
| 134 | wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c |
| 135 | #endif /* WORKAROUND_CVE_2022_23960 */ |
| 136 | |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 137 | /* -------------------------------------------------- |
| 138 | * Errata Workaround for A78C Erratum 2132064. |
| 139 | * This applies to revisions r0p1 and r0p2 of A78C |
| 140 | * and is still open. |
| 141 | * Inputs: |
| 142 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 143 | * Shall clobber: x0-x17 |
| 144 | * -------------------------------------------------- |
| 145 | */ |
| 146 | func errata_a78c_2132064_wa |
| 147 | /* Compare x0 against revisions r0p0 - r0p1 */ |
| 148 | mov x17, x30 |
| 149 | bl check_errata_2132064 |
| 150 | cbz x0, 1f |
| 151 | |
| 152 | /* -------------------------------------------------------- |
| 153 | * Place the data prefetcher in the most conservative mode |
| 154 | * to reduce prefetches by writing the following bits to |
| 155 | * the value indicated: ecltr[7:6], PF_MODE = 2'b11 |
| 156 | * -------------------------------------------------------- |
| 157 | */ |
| 158 | mrs x0, CORTEX_A78C_CPUECTLR_EL1 |
Akram Ahmad | dbff7cf | 2022-07-19 14:38:46 +0100 | [diff] [blame] | 159 | orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6 |
| 160 | orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7 |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 161 | msr CORTEX_A78C_CPUECTLR_EL1, x0 |
| 162 | isb |
| 163 | 1: |
| 164 | ret x17 |
| 165 | endfunc errata_a78c_2132064_wa |
| 166 | |
| 167 | func check_errata_2132064 |
| 168 | /* Applies to revisions r0p1 and r0p2. */ |
| 169 | mov x1, #CPU_REV(0, 1) |
| 170 | mov x2, #CPU_REV(0, 2) |
| 171 | b cpu_rev_var_range |
| 172 | endfunc check_errata_2132064 |
| 173 | |
Bipin Ravi | e0b52cc | 2023-01-18 11:03:21 -0600 | [diff] [blame] | 174 | /* ---------------------------------------------------------- |
Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 175 | * Errata Workaround for A78C Erratum 2242638. |
| 176 | * This applies to revisions r0p1 and r0p2 of the Cortex A78C |
| 177 | * processor and is still open. |
| 178 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 179 | * Shall clobber: x0-x17 |
Bipin Ravi | e0b52cc | 2023-01-18 11:03:21 -0600 | [diff] [blame] | 180 | * ---------------------------------------------------------- |
Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 181 | */ |
| 182 | func errata_a78c_2242638_wa |
| 183 | /* Compare x0 against revisions r0p1 - r0p2 */ |
| 184 | mov x17, x30 |
| 185 | bl check_errata_2242638 |
| 186 | cbz x0, 1f |
| 187 | |
| 188 | ldr x0, =0x5 |
| 189 | msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 |
| 190 | ldr x0, =0x10F600E000 |
| 191 | msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 |
| 192 | ldr x0, =0x10FF80E000 |
| 193 | msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 |
| 194 | ldr x0, =0x80000000003FF |
| 195 | msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 |
| 196 | |
| 197 | isb |
| 198 | 1: |
| 199 | ret x17 |
| 200 | endfunc errata_a78c_2242638_wa |
| 201 | |
| 202 | func check_errata_2242638 |
| 203 | /* Applies to revisions r0p1-r0p2. */ |
| 204 | mov x1, #CPU_REV(0, 1) |
| 205 | mov x2, #CPU_REV(0, 2) |
| 206 | b cpu_rev_var_range |
| 207 | endfunc check_errata_2242638 |
| 208 | |
Bipin Ravi | e0b52cc | 2023-01-18 11:03:21 -0600 | [diff] [blame] | 209 | /* ---------------------------------------------------------------- |
| 210 | * Errata Workaround for A78C Erratum 2772121. |
| 211 | * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C |
| 212 | * processor and is still open. |
| 213 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 214 | * Shall clobber: x0-x17 |
| 215 | * ---------------------------------------------------------------- |
| 216 | */ |
| 217 | func errata_a78c_2772121_wa |
| 218 | mov x17, x30 |
| 219 | bl check_errata_2772121 |
| 220 | cbz x0, 1f |
| 221 | |
| 222 | /* dsb before isb of power down sequence */ |
| 223 | dsb sy |
| 224 | 1: |
| 225 | ret x17 |
| 226 | endfunc errata_a78c_2772121_wa |
| 227 | |
| 228 | func check_errata_2772121 |
| 229 | /* Applies to all revisions <= r0p2 */ |
| 230 | mov x1, #0x02 |
| 231 | b cpu_rev_var_ls |
| 232 | endfunc check_errata_2772121 |
| 233 | |
Bipin Ravi | db09108 | 2023-02-28 16:21:51 -0600 | [diff] [blame] | 234 | /* -------------------------------------------------- |
| 235 | * Errata Workaround for Cortex A78C Errata 2779484. |
| 236 | * This applies to revisions r0p1 and r0p2. |
| 237 | * It is still open. |
| 238 | * x0: variant[4:7] and revision[0:3] of current cpu. |
| 239 | * Shall clobber: x0-x1, x17 |
| 240 | * -------------------------------------------------- |
| 241 | */ |
| 242 | func errata_a78c_2779484_wa |
| 243 | /* Check revision. */ |
| 244 | mov x17, x30 |
| 245 | bl check_errata_2779484 |
| 246 | cbz x0, 1f |
| 247 | |
| 248 | /* Apply the workaround */ |
| 249 | mrs x1, CORTEX_A78C_ACTLR3_EL1 |
| 250 | orr x1, x1, #BIT(47) |
| 251 | msr CORTEX_A78C_ACTLR3_EL1, x1 |
| 252 | |
| 253 | 1: |
| 254 | ret x17 |
| 255 | endfunc errata_a78c_2779484_wa |
| 256 | |
| 257 | func check_errata_2779484 |
| 258 | /* Applies to r0p1 and r0p2*/ |
| 259 | mov x1, #0x01 |
| 260 | mov x2, #0x02 |
| 261 | b cpu_rev_var_range |
| 262 | endfunc check_errata_2779484 |
| 263 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 264 | func check_errata_cve_2022_23960 |
| 265 | #if WORKAROUND_CVE_2022_23960 |
| 266 | mov x0, #ERRATA_APPLIES |
| 267 | #else |
| 268 | mov x0, #ERRATA_MISSING |
| 269 | #endif |
| 270 | ret |
| 271 | endfunc check_errata_cve_2022_23960 |
| 272 | |
| 273 | /* ------------------------------------------------- |
| 274 | * The CPU Ops reset function for Cortex-A78C |
| 275 | * ------------------------------------------------- |
| 276 | */ |
| 277 | func cortex_a78c_reset_func |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 278 | mov x19, x30 |
| 279 | bl cpu_get_rev_var |
| 280 | mov x18, x0 |
| 281 | |
Bipin Ravi | bf205fc | 2023-03-14 10:04:23 -0500 | [diff] [blame] | 282 | #if ERRATA_A78C_1827430 |
| 283 | mov x0, x18 |
| 284 | bl errata_a78c_1827430_wa |
| 285 | #endif |
| 286 | |
Bipin Ravi | e49c704 | 2023-03-14 11:03:24 -0500 | [diff] [blame] | 287 | #if ERRATA_A78C_1827440 |
| 288 | mov x0, x18 |
| 289 | bl errata_a78c_1827440_wa |
| 290 | #endif |
| 291 | |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 292 | #if ERRATA_A78C_2132064 |
| 293 | mov x0, x18 |
| 294 | bl errata_a78c_2132064_wa |
| 295 | #endif |
| 296 | |
Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 297 | #if ERRATA_A78C_2242638 |
| 298 | mov x0, x18 |
| 299 | bl errata_a78c_2242638_wa |
| 300 | #endif |
| 301 | |
Akram Ahmad | fbc1edb | 2022-09-06 11:23:25 +0100 | [diff] [blame] | 302 | #if ERRATA_A78C_2376749 |
| 303 | mov x0, x18 |
| 304 | bl errata_a78c_2376749_wa |
| 305 | #endif |
| 306 | |
Akram Ahmad | dbff7cf | 2022-07-19 14:38:46 +0100 | [diff] [blame] | 307 | #if ERRATA_A78C_2395411 |
| 308 | mov x0, x18 |
| 309 | bl errata_a78c_2395411_wa |
| 310 | #endif |
| 311 | |
Bipin Ravi | db09108 | 2023-02-28 16:21:51 -0600 | [diff] [blame] | 312 | #if ERRATA_A78C_2779484 |
| 313 | mov x0, x18 |
| 314 | bl errata_a78c_2779484_wa |
| 315 | #endif |
| 316 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 317 | #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 |
| 318 | /* |
| 319 | * The Cortex-A78c generic vectors are overridden to apply errata |
| 320 | * mitigation on exception entry from lower ELs. |
| 321 | */ |
| 322 | adr x0, wa_cve_vbar_cortex_a78c |
| 323 | msr vbar_el3, x0 |
| 324 | #endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */ |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 325 | |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 326 | isb |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 327 | ret x19 |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 328 | endfunc cortex_a78c_reset_func |
| 329 | |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 330 | /* ---------------------------------------------------- |
| 331 | * HW will do the cache maintenance while powering down |
| 332 | * ---------------------------------------------------- |
| 333 | */ |
| 334 | func cortex_a78c_core_pwr_dwn |
| 335 | /* --------------------------------------------------- |
| 336 | * Enable CPU power down bit in power control register |
| 337 | * --------------------------------------------------- |
| 338 | */ |
| 339 | mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1 |
| 340 | orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT |
| 341 | msr CORTEX_A78C_CPUPWRCTLR_EL1, x0 |
Bipin Ravi | e0b52cc | 2023-01-18 11:03:21 -0600 | [diff] [blame] | 342 | #if ERRATA_A78C_2772121 |
| 343 | mov x15, x30 |
| 344 | bl cpu_get_rev_var |
| 345 | bl errata_a78c_2772121_wa |
| 346 | mov x30, x15 |
| 347 | #endif /* ERRATA_A78C_2772121 */ |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 348 | isb |
| 349 | ret |
| 350 | endfunc cortex_a78c_core_pwr_dwn |
| 351 | |
| 352 | #if REPORT_ERRATA |
| 353 | /* |
| 354 | * Errata printing function for Cortex A78C. Must follow AAPCS. |
| 355 | */ |
| 356 | func cortex_a78c_errata_report |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 357 | stp x8, x30, [sp, #-16]! |
| 358 | |
| 359 | bl cpu_get_rev_var |
| 360 | mov x8, x0 |
| 361 | |
| 362 | /* |
| 363 | * Report all errata. The revision-variant information is passed to |
| 364 | * checking functions of each errata. |
| 365 | */ |
Bipin Ravi | bf205fc | 2023-03-14 10:04:23 -0500 | [diff] [blame] | 366 | report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430 |
Bipin Ravi | e49c704 | 2023-03-14 11:03:24 -0500 | [diff] [blame] | 367 | report_errata ERRATA_A78C_1827440, cortex_a78c, 1827440 |
laurenw-arm | 4dc1887 | 2022-07-12 10:43:52 -0500 | [diff] [blame] | 368 | report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 |
Bipin Ravi | 9c36e12 | 2022-07-15 17:20:16 -0500 | [diff] [blame] | 369 | report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 |
Akram Ahmad | fbc1edb | 2022-09-06 11:23:25 +0100 | [diff] [blame] | 370 | report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749 |
Akram Ahmad | dbff7cf | 2022-07-19 14:38:46 +0100 | [diff] [blame] | 371 | report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411 |
Bipin Ravi | e0b52cc | 2023-01-18 11:03:21 -0600 | [diff] [blame] | 372 | report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121 |
Bipin Ravi | db09108 | 2023-02-28 16:21:51 -0600 | [diff] [blame] | 373 | report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484 |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 374 | report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 |
| 375 | |
| 376 | ldp x8, x30, [sp], #16 |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 377 | ret |
| 378 | endfunc cortex_a78c_errata_report |
| 379 | #endif |
| 380 | |
| 381 | /* --------------------------------------------- |
| 382 | * This function provides cortex_a78c specific |
| 383 | * register information for crash reporting. |
| 384 | * It needs to return with x6 pointing to |
| 385 | * a list of register names in ascii and |
| 386 | * x8 - x15 having values of registers to be |
| 387 | * reported. |
| 388 | * --------------------------------------------- |
| 389 | */ |
| 390 | .section .rodata.cortex_a78c_regs, "aS" |
| 391 | cortex_a78c_regs: /* The ascii list of register names to be reported */ |
| 392 | .asciz "cpuectlr_el1", "" |
| 393 | |
| 394 | func cortex_a78c_cpu_reg_dump |
| 395 | adr x6, cortex_a78c_regs |
| 396 | mrs x8, CORTEX_A78C_CPUECTLR_EL1 |
| 397 | ret |
| 398 | endfunc cortex_a78c_cpu_reg_dump |
| 399 | |
| 400 | declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \ |
Bipin Ravi | eb4d12b | 2022-03-12 01:58:02 -0600 | [diff] [blame] | 401 | cortex_a78c_reset_func, \ |
Bipin Ravi | 4da1b0b | 2021-03-16 15:20:58 -0500 | [diff] [blame] | 402 | cortex_a78c_core_pwr_dwn |