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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautiere0b4fde2020-09-15 12:24:46 +02002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Yann Gautier4b0c72a2018-07-16 10:54:09 +02009#include <arch.h>
10#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/bl_common.h>
12#include <drivers/st/stm32_gpio.h>
Yann Gautier69035a82018-07-05 16:48:16 +020013
Yann Gautier038bff22019-01-17 19:17:47 +010014#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020015
16 .globl platform_mem_init
17 .globl plat_report_exception
18 .globl plat_get_my_entrypoint
19 .globl plat_secondary_cold_boot_setup
20 .globl plat_reset_handler
21 .globl plat_is_my_cpu_primary
22 .globl plat_my_core_pos
Yann Gautier69035a82018-07-05 16:48:16 +020023 .globl plat_crash_console_init
24 .globl plat_crash_console_flush
25 .globl plat_crash_console_putc
Yann Gautier4b0c72a2018-07-16 10:54:09 +020026 .globl plat_panic_handler
27
28func platform_mem_init
29 /* Nothing to do, don't need to init SYSRAM */
30 bx lr
31endfunc platform_mem_init
32
33func plat_report_exception
Yann Gautiere0b4fde2020-09-15 12:24:46 +020034#if DEBUG
35 mov r8, lr
36
37 /* Test if an abort occurred */
38 cmp r0, #MODE32_abt
39 bne undef_inst_lbl
40 ldr r4, =abort_str
41 bl asm_print_str
42 mrs r4, lr_abt
43 sub r4, r4, #4
44 b print_exception_info
45
46undef_inst_lbl:
47 /* Test for an undefined instruction */
48 cmp r0, #MODE32_und
49 bne other_exception_lbl
50 ldr r4, =undefined_str
51 bl asm_print_str
52 mrs r4, lr_und
53 b print_exception_info
54
55other_exception_lbl:
56 /* Other exceptions */
57 mov r9, r0
58 ldr r4, =exception_start_str
59 bl asm_print_str
60 mov r4, r9
61 bl asm_print_hex
62 ldr r4, =exception_end_str
63 bl asm_print_str
64 mov r4, r6
65
66print_exception_info:
67 bl asm_print_hex
68
69 ldr r4, =end_error_str
70 bl asm_print_str
71
72 bx r8
73#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +020074 bx lr
Yann Gautiere0b4fde2020-09-15 12:24:46 +020075#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020076endfunc plat_report_exception
77
78func plat_reset_handler
79 bx lr
80endfunc plat_reset_handler
81
82 /* ------------------------------------------------------------------
83 * unsigned long plat_get_my_entrypoint (void);
84 *
85 * Main job of this routine is to distinguish between a cold and warm
86 * boot.
87 *
88 * Currently supports only cold boot
89 * ------------------------------------------------------------------
90 */
91func plat_get_my_entrypoint
92 mov r0, #0
93 bx lr
94endfunc plat_get_my_entrypoint
95
96 /* ---------------------------------------------
97 * void plat_secondary_cold_boot_setup (void);
98 *
99 * Cold-booting secondary CPUs is not supported.
100 * ---------------------------------------------
101 */
102func plat_secondary_cold_boot_setup
103 b .
104endfunc plat_secondary_cold_boot_setup
105
106 /* -----------------------------------------------------
107 * unsigned int plat_is_my_cpu_primary (void);
108 *
109 * Find out whether the current cpu is the primary cpu.
110 * -----------------------------------------------------
111 */
112func plat_is_my_cpu_primary
113 ldcopr r0, MPIDR
114 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
115 and r0, r1
Yann Gautiera2e2a302019-02-14 11:13:39 +0100116 cmp r0, #STM32MP_PRIMARY_CPU
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200117 moveq r0, #1
118 movne r0, #0
119 bx lr
120endfunc plat_is_my_cpu_primary
121
122 /* -------------------------------------------
123 * int plat_stm32mp1_get_core_pos(int mpidr);
124 *
125 * Return CorePos = (ClusterId * 4) + CoreId
126 * -------------------------------------------
127 */
128func plat_stm32mp1_get_core_pos
129 and r1, r0, #MPIDR_CPU_MASK
130 and r0, r0, #MPIDR_CLUSTER_MASK
131 add r0, r1, r0, LSR #6
132 bx lr
133endfunc plat_stm32mp1_get_core_pos
134
135 /* ------------------------------------
136 * unsigned int plat_my_core_pos(void)
137 * ------------------------------------
138 */
139func plat_my_core_pos
140 ldcopr r0, MPIDR
141 b plat_stm32mp1_get_core_pos
142endfunc plat_my_core_pos
Yann Gautier69035a82018-07-05 16:48:16 +0200143
144 /* ---------------------------------------------
145 * int plat_crash_console_init(void)
146 *
147 * Initialize the crash console without a C Runtime stack.
148 * ---------------------------------------------
149 */
150func plat_crash_console_init
Yann Gautier038bff22019-01-17 19:17:47 +0100151 /* Enable GPIOs for UART TX */
152 ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
Yann Gautier69035a82018-07-05 16:48:16 +0200153 ldr r2, [r1]
Yann Gautier038bff22019-01-17 19:17:47 +0100154 /* Configure GPIO */
155 orr r2, r2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN
Yann Gautier69035a82018-07-05 16:48:16 +0200156 str r2, [r1]
Yann Gautier038bff22019-01-17 19:17:47 +0100157 ldr r1, =DEBUG_UART_TX_GPIO_BANK_ADDRESS
Yann Gautier69035a82018-07-05 16:48:16 +0200158 /* Set GPIO mode alternate */
159 ldr r2, [r1, #GPIO_MODE_OFFSET]
160 bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT)
161 orr r2, r2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT)
162 str r2, [r1, #GPIO_MODE_OFFSET]
163 /* Set GPIO speed low */
164 ldr r2, [r1, #GPIO_SPEED_OFFSET]
165 bic r2, r2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT)
166 str r2, [r1, #GPIO_SPEED_OFFSET]
167 /* Set no-pull */
168 ldr r2, [r1, #GPIO_PUPD_OFFSET]
169 bic r2, r2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT)
170 str r2, [r1, #GPIO_PUPD_OFFSET]
Yann Gautier038bff22019-01-17 19:17:47 +0100171 /* Set alternate */
Yann Gautier868007e2020-02-25 17:51:52 +0100172#if DEBUG_UART_TX_GPIO_PORT >= GPIO_ALT_LOWER_LIMIT
Yann Gautier69035a82018-07-05 16:48:16 +0200173 ldr r2, [r1, #GPIO_AFRH_OFFSET]
Yann Gautier868007e2020-02-25 17:51:52 +0100174 bic r2, r2, #(GPIO_ALTERNATE_MASK << \
175 ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2))
176 orr r2, r2, #(DEBUG_UART_TX_GPIO_ALTERNATE << \
177 ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2))
Yann Gautier69035a82018-07-05 16:48:16 +0200178 str r2, [r1, #GPIO_AFRH_OFFSET]
Yann Gautier868007e2020-02-25 17:51:52 +0100179#else
180 ldr r2, [r1, #GPIO_AFRL_OFFSET]
181 bic r2, r2, #(GPIO_ALTERNATE_MASK << (DEBUG_UART_TX_GPIO_PORT << 2))
182 orr r2, r2, #(DEBUG_UART_TX_GPIO_ALTERNATE << (DEBUG_UART_TX_GPIO_PORT << 2))
183 str r2, [r1, #GPIO_AFRL_OFFSET]
184#endif
Yann Gautier038bff22019-01-17 19:17:47 +0100185 /* Enable UART clock, with its source */
186 ldr r1, =(RCC_BASE + DEBUG_UART_TX_CLKSRC_REG)
187 mov r2, #DEBUG_UART_TX_CLKSRC
Yann Gautier69035a82018-07-05 16:48:16 +0200188 str r2, [r1]
Yann Gautier038bff22019-01-17 19:17:47 +0100189 ldr r1, =(RCC_BASE + DEBUG_UART_TX_EN_REG)
Yann Gautier69035a82018-07-05 16:48:16 +0200190 ldr r2, [r1]
Yann Gautier038bff22019-01-17 19:17:47 +0100191 orr r2, r2, #DEBUG_UART_TX_EN
Yann Gautier69035a82018-07-05 16:48:16 +0200192 str r2, [r1]
193
Yann Gautiera2e2a302019-02-14 11:13:39 +0100194 ldr r0, =STM32MP_DEBUG_USART_BASE
195 ldr r1, =STM32MP_DEBUG_USART_CLK_FRQ
196 ldr r2, =STM32MP_UART_BAUDRATE
Yann Gautier8593e442018-11-14 18:46:15 +0100197 b console_stm32_core_init
Yann Gautier69035a82018-07-05 16:48:16 +0200198endfunc plat_crash_console_init
199
200 /* ---------------------------------------------
Jimmy Brisson39f9eee2020-08-05 13:44:05 -0500201 * void plat_crash_console_flush(void)
Yann Gautier69035a82018-07-05 16:48:16 +0200202 *
203 * Flush the crash console without a C Runtime stack.
204 * ---------------------------------------------
205 */
206func plat_crash_console_flush
Yann Gautierf94d85a2020-12-09 13:35:27 +0100207 ldr r0, =STM32MP_DEBUG_USART_BASE
Yann Gautier8593e442018-11-14 18:46:15 +0100208 b console_stm32_core_flush
Yann Gautier69035a82018-07-05 16:48:16 +0200209endfunc plat_crash_console_flush
210
211 /* ---------------------------------------------
212 * int plat_crash_console_putc(int c)
213 *
214 * Print a character on the crash console without a C Runtime stack.
215 * Clobber list : r1 - r3
216 *
217 * In case of bootloading through uart, we keep console crash as this.
218 * Characters could be sent to the programmer, but will be ignored.
219 * No specific code in that case.
220 * ---------------------------------------------
221 */
222func plat_crash_console_putc
Yann Gautiera2e2a302019-02-14 11:13:39 +0100223 ldr r1, =STM32MP_DEBUG_USART_BASE
Yann Gautier8593e442018-11-14 18:46:15 +0100224 b console_stm32_core_putc
Yann Gautier69035a82018-07-05 16:48:16 +0200225endfunc plat_crash_console_putc
Yann Gautiere0b4fde2020-09-15 12:24:46 +0200226
Yann Gautiera0388f32020-09-15 12:29:53 +0200227 /* ----------------------------------------------------------
228 * void plat_panic_handler(void) __dead2;
229 * Report exception + endless loop.
230 *
231 * r6 holds the address where the fault occurred.
232 * Filling lr with this value allows debuggers to reconstruct
233 * the backtrace.
234 * ----------------------------------------------------------
235 */
236func plat_panic_handler
237 mrs r0, cpsr
238 and r0, #MODE32_MASK
239 bl plat_report_exception
240 mov lr, r6
241 b .
242endfunc plat_panic_handler
243
Yann Gautiere0b4fde2020-09-15 12:24:46 +0200244#if DEBUG
245.section .rodata.rev_err_str, "aS"
246abort_str:
247 .asciz "\nAbort at: 0x"
248undefined_str:
249 .asciz "\nUndefined instruction at: 0x"
250exception_start_str:
251 .asciz "\nException mode=0x"
252exception_end_str:
253 .asciz " at: 0x"
254end_error_str:
255 .asciz "\n\r"
256#endif