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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautier038bff22019-01-17 19:17:47 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <platform_def.h>
8
Yann Gautier4b0c72a2018-07-16 10:54:09 +02009#include <arch.h>
10#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <common/bl_common.h>
12#include <drivers/st/stm32_gpio.h>
13#include <drivers/st/stm32mp1_rcc.h>
Yann Gautier69035a82018-07-05 16:48:16 +020014
Yann Gautier038bff22019-01-17 19:17:47 +010015#define GPIO_TX_SHIFT (DEBUG_UART_TX_GPIO_PORT << 1)
16#define GPIO_TX_ALT_SHIFT ((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020017
18 .globl platform_mem_init
19 .globl plat_report_exception
20 .globl plat_get_my_entrypoint
21 .globl plat_secondary_cold_boot_setup
22 .globl plat_reset_handler
23 .globl plat_is_my_cpu_primary
24 .globl plat_my_core_pos
Yann Gautier69035a82018-07-05 16:48:16 +020025 .globl plat_crash_console_init
26 .globl plat_crash_console_flush
27 .globl plat_crash_console_putc
Yann Gautier4b0c72a2018-07-16 10:54:09 +020028 .globl plat_panic_handler
29
30func platform_mem_init
31 /* Nothing to do, don't need to init SYSRAM */
32 bx lr
33endfunc platform_mem_init
34
35func plat_report_exception
36 bx lr
37endfunc plat_report_exception
38
39func plat_reset_handler
40 bx lr
41endfunc plat_reset_handler
42
43 /* ------------------------------------------------------------------
44 * unsigned long plat_get_my_entrypoint (void);
45 *
46 * Main job of this routine is to distinguish between a cold and warm
47 * boot.
48 *
49 * Currently supports only cold boot
50 * ------------------------------------------------------------------
51 */
52func plat_get_my_entrypoint
53 mov r0, #0
54 bx lr
55endfunc plat_get_my_entrypoint
56
57 /* ---------------------------------------------
58 * void plat_secondary_cold_boot_setup (void);
59 *
60 * Cold-booting secondary CPUs is not supported.
61 * ---------------------------------------------
62 */
63func plat_secondary_cold_boot_setup
64 b .
65endfunc plat_secondary_cold_boot_setup
66
67 /* -----------------------------------------------------
68 * unsigned int plat_is_my_cpu_primary (void);
69 *
70 * Find out whether the current cpu is the primary cpu.
71 * -----------------------------------------------------
72 */
73func plat_is_my_cpu_primary
74 ldcopr r0, MPIDR
75 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
76 and r0, r1
77 cmp r0, #STM32MP1_PRIMARY_CPU
78 moveq r0, #1
79 movne r0, #0
80 bx lr
81endfunc plat_is_my_cpu_primary
82
83 /* -------------------------------------------
84 * int plat_stm32mp1_get_core_pos(int mpidr);
85 *
86 * Return CorePos = (ClusterId * 4) + CoreId
87 * -------------------------------------------
88 */
89func plat_stm32mp1_get_core_pos
90 and r1, r0, #MPIDR_CPU_MASK
91 and r0, r0, #MPIDR_CLUSTER_MASK
92 add r0, r1, r0, LSR #6
93 bx lr
94endfunc plat_stm32mp1_get_core_pos
95
96 /* ------------------------------------
97 * unsigned int plat_my_core_pos(void)
98 * ------------------------------------
99 */
100func plat_my_core_pos
101 ldcopr r0, MPIDR
102 b plat_stm32mp1_get_core_pos
103endfunc plat_my_core_pos
Yann Gautier69035a82018-07-05 16:48:16 +0200104
105 /* ---------------------------------------------
106 * int plat_crash_console_init(void)
107 *
108 * Initialize the crash console without a C Runtime stack.
109 * ---------------------------------------------
110 */
111func plat_crash_console_init
Yann Gautier038bff22019-01-17 19:17:47 +0100112 /* Enable GPIOs for UART TX */
113 ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
Yann Gautier69035a82018-07-05 16:48:16 +0200114 ldr r2, [r1]
Yann Gautier038bff22019-01-17 19:17:47 +0100115 /* Configure GPIO */
116 orr r2, r2, #DEBUG_UART_TX_GPIO_BANK_CLK_EN
Yann Gautier69035a82018-07-05 16:48:16 +0200117 str r2, [r1]
Yann Gautier038bff22019-01-17 19:17:47 +0100118 ldr r1, =DEBUG_UART_TX_GPIO_BANK_ADDRESS
Yann Gautier69035a82018-07-05 16:48:16 +0200119 /* Set GPIO mode alternate */
120 ldr r2, [r1, #GPIO_MODE_OFFSET]
121 bic r2, r2, #(GPIO_MODE_MASK << GPIO_TX_SHIFT)
122 orr r2, r2, #(GPIO_MODE_ALTERNATE << GPIO_TX_SHIFT)
123 str r2, [r1, #GPIO_MODE_OFFSET]
124 /* Set GPIO speed low */
125 ldr r2, [r1, #GPIO_SPEED_OFFSET]
126 bic r2, r2, #(GPIO_SPEED_MASK << GPIO_TX_SHIFT)
127 str r2, [r1, #GPIO_SPEED_OFFSET]
128 /* Set no-pull */
129 ldr r2, [r1, #GPIO_PUPD_OFFSET]
130 bic r2, r2, #(GPIO_PULL_MASK << GPIO_TX_SHIFT)
131 str r2, [r1, #GPIO_PUPD_OFFSET]
Yann Gautier038bff22019-01-17 19:17:47 +0100132 /* Set alternate */
Yann Gautier69035a82018-07-05 16:48:16 +0200133 ldr r2, [r1, #GPIO_AFRH_OFFSET]
134 bic r2, r2, #(GPIO_ALTERNATE_MASK << GPIO_TX_ALT_SHIFT)
Yann Gautier038bff22019-01-17 19:17:47 +0100135 orr r2, r2, #(DEBUG_UART_TX_GPIO_ALTERNATE << GPIO_TX_ALT_SHIFT)
Yann Gautier69035a82018-07-05 16:48:16 +0200136 str r2, [r1, #GPIO_AFRH_OFFSET]
Yann Gautier038bff22019-01-17 19:17:47 +0100137 /* Enable UART clock, with its source */
138 ldr r1, =(RCC_BASE + DEBUG_UART_TX_CLKSRC_REG)
139 mov r2, #DEBUG_UART_TX_CLKSRC
Yann Gautier69035a82018-07-05 16:48:16 +0200140 str r2, [r1]
Yann Gautier038bff22019-01-17 19:17:47 +0100141 ldr r1, =(RCC_BASE + DEBUG_UART_TX_EN_REG)
Yann Gautier69035a82018-07-05 16:48:16 +0200142 ldr r2, [r1]
Yann Gautier038bff22019-01-17 19:17:47 +0100143 orr r2, r2, #DEBUG_UART_TX_EN
Yann Gautier69035a82018-07-05 16:48:16 +0200144 str r2, [r1]
145
146 ldr r0, =STM32MP1_DEBUG_USART_BASE
Yann Gautier038bff22019-01-17 19:17:47 +0100147 ldr r1, =STM32MP1_DEBUG_USART_CLK_FRQ
Yann Gautier69035a82018-07-05 16:48:16 +0200148 ldr r2, =STM32MP1_UART_BAUDRATE
Yann Gautier8593e442018-11-14 18:46:15 +0100149 b console_stm32_core_init
Yann Gautier69035a82018-07-05 16:48:16 +0200150endfunc plat_crash_console_init
151
152 /* ---------------------------------------------
153 * int plat_crash_console_flush(void)
154 *
155 * Flush the crash console without a C Runtime stack.
156 * ---------------------------------------------
157 */
158func plat_crash_console_flush
159 ldr r1, =STM32MP1_DEBUG_USART_BASE
Yann Gautier8593e442018-11-14 18:46:15 +0100160 b console_stm32_core_flush
Yann Gautier69035a82018-07-05 16:48:16 +0200161endfunc plat_crash_console_flush
162
163 /* ---------------------------------------------
164 * int plat_crash_console_putc(int c)
165 *
166 * Print a character on the crash console without a C Runtime stack.
167 * Clobber list : r1 - r3
168 *
169 * In case of bootloading through uart, we keep console crash as this.
170 * Characters could be sent to the programmer, but will be ignored.
171 * No specific code in that case.
172 * ---------------------------------------------
173 */
174func plat_crash_console_putc
175 ldr r1, =STM32MP1_DEBUG_USART_BASE
Yann Gautier8593e442018-11-14 18:46:15 +0100176 b console_stm32_core_putc
Yann Gautier69035a82018-07-05 16:48:16 +0200177endfunc plat_crash_console_putc