blob: 20a94ef9e5e903587d364c6ed2c9b33733863755 [file] [log] [blame]
Nishanth Menon0192f892016-10-14 01:13:34 +00001#
2# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7# We don't use BL1 or BL2, so BL31 is the first image to execute
8RESET_TO_BL31 := 1
9# Only one core starts up at first
10COLD_BOOT_SINGLE_CPU := 1
11# We can choose where a core starts executing
12PROGRAMMABLE_RESET_ADDRESS:= 1
13
14# System coherency is managed in hardware
Andrew F. Davisf86a5de2019-04-25 14:02:33 -040015WARMBOOT_ENABLE_DCACHE_EARLY := 1
16USE_COHERENT_MEM := 1
Nishanth Menon0192f892016-10-14 01:13:34 +000017
Nishanth Menon0192f892016-10-14 01:13:34 +000018# A53 erratum for SoC. (enable them all)
19ERRATA_A53_826319 := 1
20ERRATA_A53_835769 := 1
21ERRATA_A53_836870 := 1
22ERRATA_A53_843419 := 1
23ERRATA_A53_855873 := 1
24
Nishanth Menon4f9ef162018-06-22 06:36:29 -050025# A72 Erratum for SoC
26ERRATA_A72_859971 := 1
27
Andrew F. Davis8d19f1c2019-05-14 15:38:11 -050028CRASH_REPORTING := 1
29HANDLE_EA_EL3_FIRST := 1
30
Andrew F. Davis26e89122019-01-22 14:16:03 -060031# Split out RO data into a non-executable section
32SEPARATE_CODE_AND_RODATA := 1
33
Nishanth Menonce976042016-10-14 01:13:44 +000034TI_16550_MDR_QUIRK := 1
35$(eval $(call add_define,TI_16550_MDR_QUIRK))
36
Andreas Dannenberg5e6d1402019-01-14 13:20:15 -060037# Allow customizing the UART baud rate
38K3_USART_BAUD := 115200
39$(eval $(call add_define,K3_USART_BAUD))
40
Nishanth Menon3ed1b282016-10-14 01:13:45 +000041# Libraries
42include lib/xlat_tables_v2/xlat_tables.mk
43
Nishanth Menon0192f892016-10-14 01:13:34 +000044PLAT_INCLUDES += \
45 -I${PLAT_PATH}/include \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000046 -I${PLAT_PATH}/common/drivers/sec_proxy \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +000047 -I${PLAT_PATH}/common/drivers/ti_sci \
Nishanth Menon0192f892016-10-14 01:13:34 +000048
Nishanth Menonce976042016-10-14 01:13:44 +000049K3_CONSOLE_SOURCES += \
Nishanth Menonce976042016-10-14 01:13:44 +000050 drivers/ti/uart/aarch64/16550_console.S \
51 ${PLAT_PATH}/common/k3_console.c \
52
Nishanth Menonf97ad372016-10-14 01:13:49 +000053K3_GIC_SOURCES += \
54 drivers/arm/gic/common/gic_common.c \
55 drivers/arm/gic/v3/gicv3_main.c \
56 drivers/arm/gic/v3/gicv3_helpers.c \
57 plat/common/plat_gicv3.c \
58 ${PLAT_PATH}/common/k3_gicv3.c \
59
Benjamin Faira42b61b2016-10-14 01:13:46 +000060K3_PSCI_SOURCES += \
61 plat/common/plat_psci_common.c \
62 ${PLAT_PATH}/common/k3_psci.c \
63
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000064K3_SEC_PROXY_SOURCES += \
65 ${PLAT_PATH}/common/drivers/sec_proxy/sec_proxy.c \
66
Andrew F. Davisa513b2a2018-05-04 19:06:09 +000067K3_TI_SCI_SOURCES += \
68 ${PLAT_PATH}/common/drivers/ti_sci/ti_sci.c \
69
Nishanth Menon0192f892016-10-14 01:13:34 +000070PLAT_BL_COMMON_SOURCES += \
71 lib/cpus/aarch64/cortex_a53.S \
Nishanth Menon4f9ef162018-06-22 06:36:29 -050072 lib/cpus/aarch64/cortex_a72.S \
Nishanth Menon3ed1b282016-10-14 01:13:45 +000073 ${XLAT_TABLES_LIB_SRCS} \
Nishanth Menonce976042016-10-14 01:13:44 +000074 ${K3_CONSOLE_SOURCES} \
Nishanth Menon0192f892016-10-14 01:13:34 +000075
76BL31_SOURCES += \
77 ${PLAT_PATH}/common/k3_bl31_setup.c \
Benjamin Fairf807a342016-10-18 14:32:06 -050078 ${PLAT_PATH}/common/k3_helpers.S \
Benjamin Fair42eea872016-10-14 01:13:47 +000079 ${PLAT_PATH}/common/k3_topology.c \
Nishanth Menonf97ad372016-10-14 01:13:49 +000080 ${K3_GIC_SOURCES} \
Benjamin Faira42b61b2016-10-14 01:13:46 +000081 ${K3_PSCI_SOURCES} \
Andrew F. Davis537d3ff2018-05-04 19:06:08 +000082 ${K3_SEC_PROXY_SOURCES} \
Andrew F. Davisa513b2a2018-05-04 19:06:09 +000083 ${K3_TI_SCI_SOURCES} \