fdts/stm32mp151.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (c) 2017-2024, STMicroelectronics - All Rights Reserved
 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
			nvmem-cells = <&part_number_otp>;
			nvmem-cell-names = "part_number";
		};
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	intc: interrupt-controller@a0021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xa0021000 0x1000>,
		      <0xa0022000 0x2000>;
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_csi: clk-csi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <4000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		timers12: timer@40006000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x40006000 0x400>;
			clocks = <&rcc TIM12_K>;
			clock-names = "int";
			status = "disabled";
		};

		usart2: serial@4000e000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4000e000 0x400>;
			interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART2_K>;
			resets = <&rcc USART2_R>;
			status = "disabled";
		};

		usart3: serial@4000f000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4000f000 0x400>;
			interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART3_K>;
			resets = <&rcc USART3_R>;
			status = "disabled";
		};

		uart4: serial@40010000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40010000 0x400>;
			interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART4_K>;
			resets = <&rcc UART4_R>;
			wakeup-source;
			status = "disabled";
		};

		uart5: serial@40011000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40011000 0x400>;
			interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART5_K>;
			resets = <&rcc UART5_R>;
			status = "disabled";
		};

		i2c2: i2c@40013000 {
			compatible = "st,stm32mp15-i2c";
			reg = <0x40013000 0x400>;
			interrupt-names = "event", "error";
			interrupts-extended = <&exti 22 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C2_K>;
			resets = <&rcc I2C2_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			st,syscfg-fmp = <&syscfg 0x4 0x2>;
			wakeup-source;
			status = "disabled";
		};

		uart7: serial@40018000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40018000 0x400>;
			interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART7_K>;
			resets = <&rcc UART7_R>;
			status = "disabled";
		};

		uart8: serial@40019000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40019000 0x400>;
			interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc UART8_K>;
			resets = <&rcc UART8_R>;
			status = "disabled";
		};

		usart6: serial@44003000 {
			compatible = "st,stm32h7-uart";
			reg = <0x44003000 0x400>;
			interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART6_K>;
			resets = <&rcc USART6_R>;
			status = "disabled";
		};

		timers15: timer@44006000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32-timers";
			reg = <0x44006000 0x400>;
			clocks = <&rcc TIM15_K>;
			clock-names = "int";
			status = "disabled";
		};

		usbotg_hs: usb-otg@49000000 {
			compatible = "st,stm32mp15-hsotg", "snps,dwc2";
			reg = <0x49000000 0x10000>;
			clocks = <&rcc USBO_K>;
			clock-names = "otg";
			resets = <&rcc USBO_R>;
			reset-names = "dwc2";
			interrupts-extended = <&exti 44 IRQ_TYPE_LEVEL_HIGH>;
			g-rx-fifo-size = <512>;
			g-np-tx-fifo-size = <32>;
			g-tx-fifo-size = <256 16 16 16 16 16 16 16>;
			dr_mode = "otg";
			usb33d-supply = <&usb33>;
			status = "disabled";
		};

		rcc: rcc@50000000 {
			compatible = "st,stm32mp1-rcc", "syscon";
			reg = <0x50000000 0x1000>;
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			secure-interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
			secure-interrupt-names = "wakeup";
		};

		pwr_regulators: pwr@50001000 {
			compatible = "st,stm32mp1,pwr-reg";
			reg = <0x50001000 0x10>;
			st,tzcr = <&rcc 0x0 0x1>;

			reg11: reg11 {
				regulator-name = "reg11";
				regulator-min-microvolt = <1100000>;
				regulator-max-microvolt = <1100000>;
			};

			reg18: reg18 {
				regulator-name = "reg18";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
			};

			usb33: usb33 {
				regulator-name = "usb33";
				regulator-min-microvolt = <3300000>;
				regulator-max-microvolt = <3300000>;
			};
		};

		pwr_mcu: pwr_mcu@50001014 {
			compatible = "st,stm32mp151-pwr-mcu", "syscon";
			reg = <0x50001014 0x4>;
		};

		pwr_irq: pwr@50001020 {
			compatible = "st,stm32mp1-pwr";
			reg = <0x50001020 0x100>;
			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		exti: interrupt-controller@5000d000 {
			compatible = "st,stm32mp1-exti", "syscon";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x5000d000 0x400>;

			/* exti_pwr is an extra interrupt controller used for
			 * EXTI 55 to 60. It's mapped on pwr interrupt
			 * controller.
			 */
			exti_pwr: exti-pwr {
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&pwr_irq>;
				st,irq-number = <6>;
			};
		};

		syscfg: syscon@50020000 {
			compatible = "st,stm32mp157-syscfg", "syscon";
			reg = <0x50020000 0x400>;
			clocks = <&rcc SYSCFG>;
		};

		hash1: hash@54002000 {
			compatible = "st,stm32f756-hash";
			reg = <0x54002000 0x400>;
			interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc HASH1>;
			resets = <&rcc HASH1_R>;
			status = "disabled";
		};

		rng1: rng@54003000 {
			compatible = "st,stm32-rng";
			reg = <0x54003000 0x400>;
			clocks = <&rcc RNG1_K>;
			resets = <&rcc RNG1_R>;
			status = "disabled";
		};

		fmc: memory-controller@58002000 {
			#address-cells = <2>;
			#size-cells = <1>;
			compatible = "st,stm32mp1-fmc2-ebi";
			reg = <0x58002000 0x1000>;
			clocks = <&rcc FMC_K>;
			resets = <&rcc FMC_R>;
			status = "disabled";

			ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
				 <1 0 0x64000000 0x04000000>, /* EBI CS 2 */
				 <2 0 0x68000000 0x04000000>, /* EBI CS 3 */
				 <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
				 <4 0 0x80000000 0x10000000>; /* NAND */

			nand-controller@4,0 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "st,stm32mp1-fmc2-nfc";
				reg = <4 0x00000000 0x1000>,
				      <4 0x08010000 0x1000>,
				      <4 0x08020000 0x1000>,
				      <4 0x01000000 0x1000>,
				      <4 0x09010000 0x1000>,
				      <4 0x09020000 0x1000>;
				interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
				status = "disabled";
			};
		};

		qspi: spi@58003000 {
			compatible = "st,stm32f469-qspi";
			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
			reg-names = "qspi", "qspi_mm";
			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc QSPI_K>;
			resets = <&rcc QSPI_R>;
			status = "disabled";
		};

		sdmmc1: mmc@58005000 {
			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x00253180>;
			reg = <0x58005000 0x1000>;
			interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc SDMMC1_K>;
			clock-names = "apb_pclk";
			resets = <&rcc SDMMC1_R>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <120000000>;
			status = "disabled";
		};

		sdmmc2: mmc@58007000 {
			compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
			arm,primecell-periphid = <0x00253180>;
			reg = <0x58007000 0x1000>;
			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc SDMMC2_K>;
			clock-names = "apb_pclk";
			resets = <&rcc SDMMC2_R>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <120000000>;
			status = "disabled";
		};

		iwdg2: watchdog@5a002000 {
			compatible = "st,stm32mp1-iwdg";
			reg = <0x5a002000 0x400>;
			secure-interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
			clock-names = "pclk", "lsi";
			status = "disabled";
		};

		ddr: ddr@5a003000 {
			compatible = "st,stm32mp1-ddr";
			reg = <0x5A003000 0x550 0x5A004000 0x234>;
			clocks = <&rcc AXIDCG>,
				 <&rcc DDRC1>,
				 <&rcc DDRC2>,
				 <&rcc DDRPHYC>,
				 <&rcc DDRCAPB>,
				 <&rcc DDRPHYCAPB>;
			clock-names = "axidcg",
				      "ddrc1",
				      "ddrc2",
				      "ddrphyc",
				      "ddrcapb",
				      "ddrphycapb";
			status = "okay";
		};

		usbphyc: usbphyc@5a006000 {
			#address-cells = <1>;
			#size-cells = <0>;
			#clock-cells = <0>;
			compatible = "st,stm32mp1-usbphyc";
			reg = <0x5a006000 0x1000>;
			clocks = <&rcc USBPHY_K>;
			resets = <&rcc USBPHY_R>;
			vdda1v1-supply = <&reg11>;
			vdda1v8-supply = <&reg18>;
			status = "disabled";

			usbphyc_port0: usb-phy@0 {
				#phy-cells = <0>;
				reg = <0>;
			};

			usbphyc_port1: usb-phy@1 {
				#phy-cells = <1>;
				reg = <1>;
			};
		};

		usart1: serial@5c000000 {
			compatible = "st,stm32h7-uart";
			reg = <0x5c000000 0x400>;
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc USART1_K>;
			resets = <&rcc USART1_R>;
			status = "disabled";
		};

		spi6: spi@5c001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32h7-spi";
			reg = <0x5c001000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc SPI6_K>;
			resets = <&rcc SPI6_R>;
			status = "disabled";
		};

		i2c4: i2c@5c002000 {
			compatible = "st,stm32mp15-i2c";
			reg = <0x5c002000 0x400>;
			interrupt-names = "event", "error";
			interrupts-extended = <&exti 24 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C4_K>;
			resets = <&rcc I2C4_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			st,syscfg-fmp = <&syscfg 0x4 0x8>;
			wakeup-source;
			status = "disabled";
		};

		iwdg1: watchdog@5c003000 {
			compatible = "st,stm32mp1-iwdg";
			reg = <0x5C003000 0x400>;
			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc IWDG1>, <&rcc CK_LSI>;
			clock-names = "pclk", "lsi";
			status = "disabled";
		};

		rtc: rtc@5c004000 {
			compatible = "st,stm32mp1-rtc";
			reg = <0x5c004000 0x400>;
			clocks = <&rcc RTCAPB>, <&rcc RTC>;
			clock-names = "pclk", "rtc_ck";
			interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		bsec: efuse@5c005000 {
			compatible = "st,stm32mp15-bsec";
			reg = <0x5c005000 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;

			cfg0_otp: cfg0-otp@0 {
				reg = <0x0 0x1>;
			};
			part_number_otp: part-number-otp@4 {
				reg = <0x4 0x1>;
			};
			monotonic_otp: monotonic-otp@10 {
				reg = <0x10 0x4>;
			};
			nand_otp: nand-otp@24 {
				reg = <0x24 0x4>;
			};
			uid_otp: uid-otp@34 {
				reg = <0x34 0xc>;
			};
			package_otp: package-otp@40 {
				reg = <0x40 0x4>;
			};
			hw2_otp: hw2-otp@48 {
				reg = <0x48 0x4>;
			};
			ts_cal1: calib@5c {
				reg = <0x5c 0x2>;
			};
			ts_cal2: calib@5e {
				reg = <0x5e 0x2>;
			};
			pkh_otp: pkh-otp@60 {
				reg = <0x60 0x20>;
			};
			ethernet_mac_address: mac@e4 {
				reg = <0xe4 0x8>;
				st,non-secure-otp;
			};
		};

		etzpc: etzpc@5c007000 {
			compatible = "st,stm32-etzpc";
			reg = <0x5C007000 0x400>;
			clocks = <&rcc TZPC>;
		};

		stgen: stgen@5c008000 {
			compatible = "st,stm32-stgen";
			reg = <0x5C008000 0x1000>;
		};

		i2c6: i2c@5c009000 {
			compatible = "st,stm32mp15-i2c";
			reg = <0x5c009000 0x400>;
			interrupt-names = "event", "error";
			interrupts-extended = <&exti 54 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc I2C6_K>;
			resets = <&rcc I2C6_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			st,syscfg-fmp = <&syscfg 0x4 0x20>;
			wakeup-source;
			status = "disabled";
		};

		tamp: tamp@5c00a000 {
			compatible = "st,stm32-tamp", "syscon", "simple-mfd";
			reg = <0x5c00a000 0x400>;
			secure-interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc RTCAPB>;
		};

		/*
		 * Break node order to solve dependency probe issue between
		 * pinctrl and exti.
		 */
		pinctrl: pinctrl@50002000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp157-pinctrl";
			ranges = <0 0x50002000 0xa400>;
			interrupt-parent = <&exti>;
			st,syscfg = <&exti 0x60 0xff>;

			gpioa: gpio@50002000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x0 0x400>;
				clocks = <&rcc GPIOA>;
				st,bank-name = "GPIOA";
				status = "disabled";
			};

			gpiob: gpio@50003000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x1000 0x400>;
				clocks = <&rcc GPIOB>;
				st,bank-name = "GPIOB";
				status = "disabled";
			};

			gpioc: gpio@50004000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x2000 0x400>;
				clocks = <&rcc GPIOC>;
				st,bank-name = "GPIOC";
				status = "disabled";
			};

			gpiod: gpio@50005000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x3000 0x400>;
				clocks = <&rcc GPIOD>;
				st,bank-name = "GPIOD";
				status = "disabled";
			};

			gpioe: gpio@50006000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x4000 0x400>;
				clocks = <&rcc GPIOE>;
				st,bank-name = "GPIOE";
				status = "disabled";
			};

			gpiof: gpio@50007000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x5000 0x400>;
				clocks = <&rcc GPIOF>;
				st,bank-name = "GPIOF";
				status = "disabled";
			};

			gpiog: gpio@50008000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x6000 0x400>;
				clocks = <&rcc GPIOG>;
				st,bank-name = "GPIOG";
				status = "disabled";
			};

			gpioh: gpio@50009000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x7000 0x400>;
				clocks = <&rcc GPIOH>;
				st,bank-name = "GPIOH";
				status = "disabled";
			};

			gpioi: gpio@5000a000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x8000 0x400>;
				clocks = <&rcc GPIOI>;
				st,bank-name = "GPIOI";
				status = "disabled";
			};

			gpioj: gpio@5000b000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0x9000 0x400>;
				clocks = <&rcc GPIOJ>;
				st,bank-name = "GPIOJ";
				status = "disabled";
			};

			gpiok: gpio@5000c000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0xa000 0x400>;
				clocks = <&rcc GPIOK>;
				st,bank-name = "GPIOK";
				status = "disabled";
			};
		};

		pinctrl_z: pinctrl@54004000 {
			#address-cells = <1>;
			#size-cells = <1>;
			compatible = "st,stm32mp157-z-pinctrl";
			ranges = <0 0x54004000 0x400>;
			interrupt-parent = <&exti>;
			st,syscfg = <&exti 0x60 0xff>;

			gpioz: gpio@54004000 {
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg = <0 0x400>;
				clocks = <&rcc GPIOZ>;
				st,bank-name = "GPIOZ";
				st,bank-ioport = <11>;
				status = "disabled";
			};
		};
	};
};