Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <arch_helpers.h> |
| 33 | #include <assert.h> |
| 34 | #include <bl_common.h> |
| 35 | #include <bl31.h> |
| 36 | #include <debug.h> |
| 37 | #include <context_mgmt.h> |
| 38 | #include <platform.h> |
| 39 | #include <runtime_svc.h> |
| 40 | #include <stddef.h> |
| 41 | #include "psci_private.h" |
| 42 | |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 43 | /******************************************************************************* |
| 44 | * This function checks whether a cpu which has been requested to be turned on |
| 45 | * is OFF to begin with. |
| 46 | ******************************************************************************/ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 47 | static int cpu_on_validate_state(aff_info_state_t aff_state) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 48 | { |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 49 | if (aff_state == AFF_STATE_ON) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 50 | return PSCI_E_ALREADY_ON; |
| 51 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 52 | if (aff_state == AFF_STATE_ON_PENDING) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 53 | return PSCI_E_ON_PENDING; |
| 54 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 55 | assert(aff_state == AFF_STATE_OFF); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 56 | return PSCI_E_SUCCESS; |
| 57 | } |
| 58 | |
| 59 | /******************************************************************************* |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 60 | * Generic handler which is called to physically power on a cpu identified by |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 61 | * its mpidr. It performs the generic, architectural, platform setup and state |
| 62 | * management to power on the target cpu e.g. it will ensure that |
| 63 | * enough information is stashed for it to resume execution in the non-secure |
| 64 | * security state. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 65 | * |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 66 | * The state of all the relevant power domains are changed after calling the |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 67 | * platform handler as it can return error. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 68 | ******************************************************************************/ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 69 | int psci_cpu_on_start(u_register_t target_cpu, |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 70 | entry_point_info_t *ep, |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 71 | unsigned int end_pwrlvl) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 72 | { |
| 73 | int rc; |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 74 | unsigned int target_idx = plat_core_pos_by_mpidr(target_cpu); |
Soby Mathew | ca37050 | 2016-01-26 11:47:53 +0000 | [diff] [blame] | 75 | aff_info_state_t target_aff_state; |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 76 | |
| 77 | /* |
| 78 | * This function must only be called on platforms where the |
| 79 | * CPU_ON platform hooks have been implemented. |
| 80 | */ |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 81 | assert(psci_plat_pm_ops->pwr_domain_on && |
| 82 | psci_plat_pm_ops->pwr_domain_on_finish); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 83 | |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 84 | /* Protect against multiple CPUs trying to turn ON the same target CPU */ |
| 85 | psci_spin_lock_cpu(target_idx); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 86 | |
| 87 | /* |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 88 | * Generic management: Ensure that the cpu is off to be |
| 89 | * turned on. |
| 90 | */ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 91 | rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx)); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 92 | if (rc != PSCI_E_SUCCESS) |
| 93 | goto exit; |
| 94 | |
| 95 | /* |
| 96 | * Call the cpu on handler registered by the Secure Payload Dispatcher |
| 97 | * to let it do any bookeeping. If the handler encounters an error, it's |
| 98 | * expected to assert within |
| 99 | */ |
| 100 | if (psci_spd_pm && psci_spd_pm->svc_on) |
| 101 | psci_spd_pm->svc_on(target_cpu); |
| 102 | |
| 103 | /* |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 104 | * Set the Affinity info state of the target cpu to ON_PENDING. |
Soby Mathew | ca37050 | 2016-01-26 11:47:53 +0000 | [diff] [blame] | 105 | * Flush aff_info_state as it will be accessed with caches |
| 106 | * turned OFF. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 107 | */ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 108 | psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); |
Soby Mathew | ca37050 | 2016-01-26 11:47:53 +0000 | [diff] [blame] | 109 | flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); |
| 110 | |
| 111 | /* |
| 112 | * The cache line invalidation by the target CPU after setting the |
| 113 | * state to OFF (see psci_do_cpu_off()), could cause the update to |
| 114 | * aff_info_state to be invalidated. Retry the update if the target |
| 115 | * CPU aff_info_state is not ON_PENDING. |
| 116 | */ |
| 117 | target_aff_state = psci_get_aff_info_state_by_idx(target_idx); |
| 118 | if (target_aff_state != AFF_STATE_ON_PENDING) { |
| 119 | assert(target_aff_state == AFF_STATE_OFF); |
| 120 | psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING); |
| 121 | flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); |
| 122 | |
| 123 | assert(psci_get_aff_info_state_by_idx(target_idx) == AFF_STATE_ON_PENDING); |
| 124 | } |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 125 | |
| 126 | /* |
| 127 | * Perform generic, architecture and platform specific handling. |
| 128 | */ |
Soby Mathew | 6b8b302 | 2015-06-30 11:00:24 +0100 | [diff] [blame] | 129 | /* |
| 130 | * Plat. management: Give the platform the current state |
| 131 | * of the target cpu to allow it to perform the necessary |
| 132 | * steps to power on. |
| 133 | */ |
Soby Mathew | 011ca18 | 2015-07-29 17:05:03 +0100 | [diff] [blame] | 134 | rc = psci_plat_pm_ops->pwr_domain_on(target_cpu); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 135 | assert(rc == PSCI_E_SUCCESS || rc == PSCI_E_INTERN_FAIL); |
| 136 | |
| 137 | if (rc == PSCI_E_SUCCESS) |
| 138 | /* Store the re-entry information for the non-secure world. */ |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 139 | cm_init_context_by_index(target_idx, ep); |
Soby Mathew | ca37050 | 2016-01-26 11:47:53 +0000 | [diff] [blame] | 140 | else { |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 141 | /* Restore the state on error. */ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 142 | psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF); |
Soby Mathew | ca37050 | 2016-01-26 11:47:53 +0000 | [diff] [blame] | 143 | flush_cpu_data_by_index(target_idx, psci_svc_cpu_data.aff_info_state); |
| 144 | } |
Soby Mathew | b0082d2 | 2015-04-09 13:40:55 +0100 | [diff] [blame] | 145 | |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 146 | exit: |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 147 | psci_spin_unlock_cpu(target_idx); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 148 | return rc; |
| 149 | } |
| 150 | |
| 151 | /******************************************************************************* |
Soby Mathew | 3a9e8bf | 2015-05-05 16:33:16 +0100 | [diff] [blame] | 152 | * The following function finish an earlier power on request. They |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 153 | * are called by the common finisher routine in psci_common.c. The `state_info` |
| 154 | * is the psci_power_state from which this CPU has woken up from. |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 155 | ******************************************************************************/ |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 156 | void psci_cpu_on_finish(unsigned int cpu_idx, |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 157 | psci_power_state_t *state_info) |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 158 | { |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 159 | /* |
| 160 | * Plat. management: Perform the platform specific actions |
| 161 | * for this cpu e.g. enabling the gic or zeroing the mailbox |
| 162 | * register. The actual state of this cpu has already been |
| 163 | * changed. |
| 164 | */ |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 165 | psci_plat_pm_ops->pwr_domain_on_finish(state_info); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 166 | |
| 167 | /* |
| 168 | * Arch. management: Enable data cache and manage stack memory |
| 169 | */ |
| 170 | psci_do_pwrup_cache_maintenance(); |
| 171 | |
| 172 | /* |
| 173 | * All the platform specific actions for turning this cpu |
| 174 | * on have completed. Perform enough arch.initialization |
| 175 | * to run in the non-secure address space. |
| 176 | */ |
| 177 | bl31_arch_setup(); |
| 178 | |
| 179 | /* |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 180 | * Lock the CPU spin lock to make sure that the context initialization |
| 181 | * is done. Since the lock is only used in this function to create |
| 182 | * a synchronization point with cpu_on_start(), it can be released |
| 183 | * immediately. |
| 184 | */ |
| 185 | psci_spin_lock_cpu(cpu_idx); |
| 186 | psci_spin_unlock_cpu(cpu_idx); |
| 187 | |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 188 | /* Ensure we have been explicitly woken up by another cpu */ |
| 189 | assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING); |
| 190 | |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 191 | /* |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 192 | * Call the cpu on finish handler registered by the Secure Payload |
| 193 | * Dispatcher to let it do any bookeeping. If the handler encounters an |
| 194 | * error, it's expected to assert within |
| 195 | */ |
| 196 | if (psci_spd_pm && psci_spd_pm->svc_on_finish) |
| 197 | psci_spd_pm->svc_on_finish(0); |
| 198 | |
Soby Mathew | 9d754f6 | 2015-04-08 17:42:06 +0100 | [diff] [blame] | 199 | /* Populate the mpidr field within the cpu node array */ |
| 200 | /* This needs to be done only once */ |
| 201 | psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK; |
| 202 | |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 203 | /* |
| 204 | * Generic management: Now we just need to retrieve the |
| 205 | * information that we had stashed away during the cpu_on |
| 206 | * call to set this cpu on its way. |
| 207 | */ |
| 208 | cm_prepare_el3_exit(NON_SECURE); |
Soby Mathew | 991d42c | 2015-06-29 16:30:12 +0100 | [diff] [blame] | 209 | } |