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Achin Gupta9ac63c52014-01-16 12:08:03 +00001/*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __CONTEXT_H__
32#define __CONTEXT_H__
33
Achin Gupta9ac63c52014-01-16 12:08:03 +000034/*******************************************************************************
Achin Gupta07f4e072014-02-02 12:02:23 +000035 * Constants that allow assembler code to access members of and the 'gp_regs'
36 * structure at their correct offsets.
37 ******************************************************************************/
38#define CTX_GPREGS_OFFSET 0x0
39#define CTX_GPREG_X0 0x0
40#define CTX_GPREG_X1 0x8
41#define CTX_GPREG_X2 0x10
42#define CTX_GPREG_X3 0x18
43#define CTX_GPREG_X4 0x20
44#define CTX_GPREG_X5 0x28
45#define CTX_GPREG_X6 0x30
46#define CTX_GPREG_X7 0x38
47#define CTX_GPREG_X8 0x40
48#define CTX_GPREG_X9 0x48
49#define CTX_GPREG_X10 0x50
50#define CTX_GPREG_X11 0x58
51#define CTX_GPREG_X12 0x60
52#define CTX_GPREG_X13 0x68
53#define CTX_GPREG_X14 0x70
54#define CTX_GPREG_X15 0x78
55#define CTX_GPREG_X16 0x80
56#define CTX_GPREG_X17 0x88
57#define CTX_GPREG_X18 0x90
Soby Mathew6c5192a2014-04-30 15:36:37 +010058#define CTX_GPREG_X19 0x98
59#define CTX_GPREG_X20 0xa0
60#define CTX_GPREG_X21 0xa8
61#define CTX_GPREG_X22 0xb0
62#define CTX_GPREG_X23 0xb8
63#define CTX_GPREG_X24 0xc0
64#define CTX_GPREG_X25 0xc8
65#define CTX_GPREG_X26 0xd0
66#define CTX_GPREG_X27 0xd8
67#define CTX_GPREG_X28 0xe0
68#define CTX_GPREG_X29 0xe8
69#define CTX_GPREG_LR 0xf0
70#define CTX_GPREG_SP_EL0 0xf8
71#define CTX_GPREGS_END 0x100
Achin Gupta07f4e072014-02-02 12:02:23 +000072
73/*******************************************************************************
Achin Gupta9ac63c52014-01-16 12:08:03 +000074 * Constants that allow assembler code to access members of and the 'el3_state'
75 * structure at their correct offsets. Note that some of the registers are only
76 * 32-bits wide but are stored as 64-bit values for convenience
77 ******************************************************************************/
Achin Gupta07f4e072014-02-02 12:02:23 +000078#define CTX_EL3STATE_OFFSET (CTX_GPREGS_OFFSET + CTX_GPREGS_END)
Achin Guptae1aa5162014-06-26 09:58:52 +010079#define CTX_SCR_EL3 0x0
Achin Gupta07f4e072014-02-02 12:02:23 +000080#define CTX_RUNTIME_SP 0x8
Achin Gupta9ac63c52014-01-16 12:08:03 +000081#define CTX_SPSR_EL3 0x10
82#define CTX_ELR_EL3 0x18
Soby Mathew2ed46e92014-07-04 16:02:26 +010083#define CTX_EL3STATE_END 0x20
Achin Gupta9ac63c52014-01-16 12:08:03 +000084
85/*******************************************************************************
86 * Constants that allow assembler code to access members of and the
87 * 'el1_sys_regs' structure at their correct offsets. Note that some of the
88 * registers are only 32-bits wide but are stored as 64-bit values for
89 * convenience
90 ******************************************************************************/
91#define CTX_SYSREGS_OFFSET (CTX_EL3STATE_OFFSET + CTX_EL3STATE_END)
92#define CTX_SPSR_EL1 0x0
93#define CTX_ELR_EL1 0x8
94#define CTX_SPSR_ABT 0x10
95#define CTX_SPSR_UND 0x18
96#define CTX_SPSR_IRQ 0x20
97#define CTX_SPSR_FIQ 0x28
98#define CTX_SCTLR_EL1 0x30
99#define CTX_ACTLR_EL1 0x38
100#define CTX_CPACR_EL1 0x40
101#define CTX_CSSELR_EL1 0x48
102#define CTX_SP_EL1 0x50
103#define CTX_ESR_EL1 0x58
104#define CTX_TTBR0_EL1 0x60
105#define CTX_TTBR1_EL1 0x68
106#define CTX_MAIR_EL1 0x70
107#define CTX_AMAIR_EL1 0x78
108#define CTX_TCR_EL1 0x80
109#define CTX_TPIDR_EL1 0x88
110#define CTX_TPIDR_EL0 0x90
111#define CTX_TPIDRRO_EL0 0x98
112#define CTX_DACR32_EL2 0xa0
113#define CTX_IFSR32_EL2 0xa8
114#define CTX_PAR_EL1 0xb0
115#define CTX_FAR_EL1 0xb8
116#define CTX_AFSR0_EL1 0xc0
117#define CTX_AFSR1_EL1 0xc8
118#define CTX_CONTEXTIDR_EL1 0xd0
119#define CTX_VBAR_EL1 0xd8
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100120/*
121 * If the timer registers aren't saved and restored, we don't have to reserve
122 * space for them in the context
123 */
124#if NS_TIMER_SWITCH
Achin Gupta9ac63c52014-01-16 12:08:03 +0000125#define CTX_CNTP_CTL_EL0 0xe0
126#define CTX_CNTP_CVAL_EL0 0xe8
127#define CTX_CNTV_CTL_EL0 0xf0
128#define CTX_CNTV_CVAL_EL0 0xf8
129#define CTX_CNTKCTL_EL1 0x100
130#define CTX_FP_FPEXC32_EL2 0x108
131#define CTX_SYSREGS_END 0x110
Jeenu Viswambharand1b60152014-05-12 15:28:47 +0100132#else
133#define CTX_FP_FPEXC32_EL2 0xe0
134#define CTX_SYSREGS_END 0xf0
135#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000136
137/*******************************************************************************
138 * Constants that allow assembler code to access members of and the 'fp_regs'
139 * structure at their correct offsets.
140 ******************************************************************************/
Juan Castillo258e94f2014-06-25 17:26:36 +0100141#if CTX_INCLUDE_FPREGS
Achin Gupta9ac63c52014-01-16 12:08:03 +0000142#define CTX_FPREGS_OFFSET (CTX_SYSREGS_OFFSET + CTX_SYSREGS_END)
143#define CTX_FP_Q0 0x0
144#define CTX_FP_Q1 0x10
145#define CTX_FP_Q2 0x20
146#define CTX_FP_Q3 0x30
147#define CTX_FP_Q4 0x40
148#define CTX_FP_Q5 0x50
149#define CTX_FP_Q6 0x60
150#define CTX_FP_Q7 0x70
151#define CTX_FP_Q8 0x80
152#define CTX_FP_Q9 0x90
153#define CTX_FP_Q10 0xa0
154#define CTX_FP_Q11 0xb0
155#define CTX_FP_Q12 0xc0
156#define CTX_FP_Q13 0xd0
157#define CTX_FP_Q14 0xe0
158#define CTX_FP_Q15 0xf0
159#define CTX_FP_Q16 0x100
160#define CTX_FP_Q17 0x110
161#define CTX_FP_Q18 0x120
162#define CTX_FP_Q19 0x130
163#define CTX_FP_Q20 0x140
164#define CTX_FP_Q21 0x150
165#define CTX_FP_Q22 0x160
166#define CTX_FP_Q23 0x170
167#define CTX_FP_Q24 0x180
168#define CTX_FP_Q25 0x190
169#define CTX_FP_Q26 0x1a0
170#define CTX_FP_Q27 0x1b0
171#define CTX_FP_Q28 0x1c0
172#define CTX_FP_Q29 0x1d0
173#define CTX_FP_Q30 0x1e0
174#define CTX_FP_Q31 0x1f0
175#define CTX_FP_FPSR 0x200
176#define CTX_FP_FPCR 0x208
177#define CTX_FPREGS_END 0x210
Juan Castillo258e94f2014-06-25 17:26:36 +0100178#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000179
180#ifndef __ASSEMBLY__
181
Dan Handley2bd4ef22014-04-09 13:14:54 +0100182#include <cassert.h>
Andrew Thoelkec02dbd62014-06-02 10:00:25 +0100183#include <platform_def.h> /* for CACHE_WRITEBACK_GRANULE */
Dan Handley2bd4ef22014-04-09 13:14:54 +0100184#include <stdint.h>
185
Achin Gupta9ac63c52014-01-16 12:08:03 +0000186/*
187 * Common constants to help define the 'cpu_context' structure and its
188 * members below.
189 */
190#define DWORD_SHIFT 3
191#define DEFINE_REG_STRUCT(name, num_regs) \
Dan Handleye2712bc2014-04-10 15:37:22 +0100192 typedef struct name { \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000193 uint64_t _regs[num_regs]; \
Dan Handleye2712bc2014-04-10 15:37:22 +0100194 } __aligned(16) name##_t
Achin Gupta9ac63c52014-01-16 12:08:03 +0000195
196/* Constants to determine the size of individual context structures */
Achin Gupta07f4e072014-02-02 12:02:23 +0000197#define CTX_GPREG_ALL (CTX_GPREGS_END >> DWORD_SHIFT)
Achin Gupta9ac63c52014-01-16 12:08:03 +0000198#define CTX_SYSREG_ALL (CTX_SYSREGS_END >> DWORD_SHIFT)
Juan Castillo258e94f2014-06-25 17:26:36 +0100199#if CTX_INCLUDE_FPREGS
Achin Gupta9ac63c52014-01-16 12:08:03 +0000200#define CTX_FPREG_ALL (CTX_FPREGS_END >> DWORD_SHIFT)
Juan Castillo258e94f2014-06-25 17:26:36 +0100201#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000202#define CTX_EL3STATE_ALL (CTX_EL3STATE_END >> DWORD_SHIFT)
203
204/*
Soby Mathew6c5192a2014-04-30 15:36:37 +0100205 * AArch64 general purpose register context structure. Usually x0-x18,
206 * lr are saved as the compiler is expected to preserve the remaining
Achin Gupta07f4e072014-02-02 12:02:23 +0000207 * callee saved registers if used by the C runtime and the assembler
Soby Mathew6c5192a2014-04-30 15:36:37 +0100208 * does not touch the remaining. But in case of world switch during
209 * exception handling, we need to save the callee registers too.
Achin Gupta07f4e072014-02-02 12:02:23 +0000210 */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000211DEFINE_REG_STRUCT(gp_regs, CTX_GPREG_ALL);
Achin Gupta07f4e072014-02-02 12:02:23 +0000212
213/*
Achin Gupta9ac63c52014-01-16 12:08:03 +0000214 * AArch64 EL1 system register context structure for preserving the
215 * architectural state during switches from one security state to
216 * another in EL1.
217 */
218DEFINE_REG_STRUCT(el1_sys_regs, CTX_SYSREG_ALL);
219
220/*
221 * AArch64 floating point register context structure for preserving
222 * the floating point state during switches from one security state to
223 * another.
224 */
Juan Castillo258e94f2014-06-25 17:26:36 +0100225#if CTX_INCLUDE_FPREGS
Achin Gupta9ac63c52014-01-16 12:08:03 +0000226DEFINE_REG_STRUCT(fp_regs, CTX_FPREG_ALL);
Juan Castillo258e94f2014-06-25 17:26:36 +0100227#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000228
229/*
230 * Miscellaneous registers used by EL3 firmware to maintain its state
231 * across exception entries and exits
232 */
233DEFINE_REG_STRUCT(el3_state, CTX_EL3STATE_ALL);
234
235/*
236 * Macros to access members of any of the above structures using their
237 * offsets
238 */
239#define read_ctx_reg(ctx, offset) ((ctx)->_regs[offset >> DWORD_SHIFT])
240#define write_ctx_reg(ctx, offset, val) (((ctx)->_regs[offset >> DWORD_SHIFT]) \
241 = val)
242
243/*
244 * Top-level context structure which is used by EL3 firmware to
245 * preserve the state of a core at EL1 in one of the two security
246 * states and save enough EL3 meta data to be able to return to that
247 * EL and security state. The context management library will be used
248 * to ensure that SP_EL3 always points to an instance of this
249 * structure at exception entry and exit. Each instance will
250 * correspond to either the secure or the non-secure state.
251 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100252typedef struct cpu_context {
253 gp_regs_t gpregs_ctx;
254 el3_state_t el3state_ctx;
255 el1_sys_regs_t sysregs_ctx;
Juan Castillo258e94f2014-06-25 17:26:36 +0100256#if CTX_INCLUDE_FPREGS
Dan Handleye2712bc2014-04-10 15:37:22 +0100257 fp_regs_t fpregs_ctx;
Juan Castillo258e94f2014-06-25 17:26:36 +0100258#endif
Dan Handleye2712bc2014-04-10 15:37:22 +0100259} cpu_context_t;
Achin Gupta9ac63c52014-01-16 12:08:03 +0000260
Dan Handleye2712bc2014-04-10 15:37:22 +0100261/* Macros to access members of the 'cpu_context_t' structure */
262#define get_el3state_ctx(h) (&((cpu_context_t *) h)->el3state_ctx)
Juan Castillo258e94f2014-06-25 17:26:36 +0100263#if CTX_INCLUDE_FPREGS
Dan Handleye2712bc2014-04-10 15:37:22 +0100264#define get_fpregs_ctx(h) (&((cpu_context_t *) h)->fpregs_ctx)
Juan Castillo258e94f2014-06-25 17:26:36 +0100265#endif
Dan Handleye2712bc2014-04-10 15:37:22 +0100266#define get_sysregs_ctx(h) (&((cpu_context_t *) h)->sysregs_ctx)
267#define get_gpregs_ctx(h) (&((cpu_context_t *) h)->gpregs_ctx)
Achin Gupta9ac63c52014-01-16 12:08:03 +0000268
269/*
270 * Compile time assertions related to the 'cpu_context' structure to
271 * ensure that the assembler and the compiler view of the offsets of
272 * the structure members is the same.
273 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100274CASSERT(CTX_GPREGS_OFFSET == __builtin_offsetof(cpu_context_t, gpregs_ctx), \
Achin Gupta07f4e072014-02-02 12:02:23 +0000275 assert_core_context_gp_offset_mismatch);
Dan Handleye2712bc2014-04-10 15:37:22 +0100276CASSERT(CTX_SYSREGS_OFFSET == __builtin_offsetof(cpu_context_t, sysregs_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000277 assert_core_context_sys_offset_mismatch);
Juan Castillo258e94f2014-06-25 17:26:36 +0100278#if CTX_INCLUDE_FPREGS
Dan Handleye2712bc2014-04-10 15:37:22 +0100279CASSERT(CTX_FPREGS_OFFSET == __builtin_offsetof(cpu_context_t, fpregs_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000280 assert_core_context_fp_offset_mismatch);
Juan Castillo258e94f2014-06-25 17:26:36 +0100281#endif
Dan Handleye2712bc2014-04-10 15:37:22 +0100282CASSERT(CTX_EL3STATE_OFFSET == __builtin_offsetof(cpu_context_t, el3state_ctx), \
Achin Gupta9ac63c52014-01-16 12:08:03 +0000283 assert_core_context_el3state_offset_mismatch);
284
Achin Gupta607084e2014-02-09 18:24:19 +0000285/*
286 * Helper macro to set the general purpose registers that correspond to
287 * parameters in an aapcs_64 call i.e. x0-x7
288 */
289#define set_aapcs_args0(ctx, x0) do { \
290 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, x0); \
291 } while (0);
292#define set_aapcs_args1(ctx, x0, x1) do { \
293 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X1, x1); \
294 set_aapcs_args0(ctx, x0); \
295 } while (0);
296#define set_aapcs_args2(ctx, x0, x1, x2) do { \
297 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X2, x2); \
298 set_aapcs_args1(ctx, x0, x1); \
299 } while (0);
300#define set_aapcs_args3(ctx, x0, x1, x2, x3) do { \
301 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X3, x3); \
302 set_aapcs_args2(ctx, x0, x1, x2); \
303 } while (0);
304#define set_aapcs_args4(ctx, x0, x1, x2, x3, x4) do { \
305 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X4, x4); \
306 set_aapcs_args3(ctx, x0, x1, x2, x3); \
307 } while (0);
308#define set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5) do { \
309 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5, x5); \
310 set_aapcs_args4(ctx, x0, x1, x2, x3, x4); \
311 } while (0);
312#define set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6) do { \
313 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X6, x6); \
314 set_aapcs_args5(ctx, x0, x1, x2, x3, x4, x5); \
315 } while (0);
316#define set_aapcs_args7(ctx, x0, x1, x2, x3, x4, x5, x6, x7) do { \
317 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X7, x7); \
318 set_aapcs_args6(ctx, x0, x1, x2, x3, x4, x5, x6); \
319 } while (0);
320
Achin Gupta9ac63c52014-01-16 12:08:03 +0000321/*******************************************************************************
322 * Function prototypes
323 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100324void el1_sysregs_context_save(el1_sys_regs_t *regs);
325void el1_sysregs_context_restore(el1_sys_regs_t *regs);
Juan Castillo258e94f2014-06-25 17:26:36 +0100326#if CTX_INCLUDE_FPREGS
Dan Handleye2712bc2014-04-10 15:37:22 +0100327void fpregs_context_save(fp_regs_t *regs);
328void fpregs_context_restore(fp_regs_t *regs);
Juan Castillo258e94f2014-06-25 17:26:36 +0100329#endif
Achin Gupta9ac63c52014-01-16 12:08:03 +0000330
Soby Mathew5e5c2072014-04-07 15:28:55 +0100331
Achin Gupta9ac63c52014-01-16 12:08:03 +0000332#undef CTX_SYSREG_ALL
Juan Castillo258e94f2014-06-25 17:26:36 +0100333#if CTX_INCLUDE_FPREGS
334#undef CTX_FPREG_ALL
335#endif
Achin Gupta07f4e072014-02-02 12:02:23 +0000336#undef CTX_GPREG_ALL
Achin Gupta9ac63c52014-01-16 12:08:03 +0000337#undef CTX_EL3STATE_ALL
338
339#endif /* __ASSEMBLY__ */
340
341#endif /* __CONTEXT_H__ */