blob: e8110b041a549e71cca48b971127443ce99c6ecc [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Robert Wakim48e6b572021-10-21 15:39:56 +01002 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handley2bd4ef22014-04-09 13:14:54 +01007#include <arch.h>
Andrew Thoelke38bde412014-03-18 13:46:55 +00008#include <asm_macros.S>
Soby Mathew041f62a2014-07-14 16:58:03 +01009#include <assert_macros.S>
Varun Wadekar17425d32019-01-10 15:46:34 -080010#include <common/bl_common.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4a826dd2013-11-25 14:00:56 +000012
Achin Gupta4f6ad662013-10-25 09:08:21 +010013 .globl smc
14
Douglas Raillard21362a92016-12-02 13:51:54 +000015 .globl zero_normalmem
16 .globl zeromem
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000017 .globl memcpy16
Robert Wakim48e6b572021-10-21 15:39:56 +010018 .globl gpt_tlbi_by_pa_ll
Achin Gupta4f6ad662013-10-25 09:08:21 +010019
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +010020 .globl disable_mmu_el1
Andrew Thoelke438c63a2014-04-28 12:06:18 +010021 .globl disable_mmu_el3
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +010022 .globl disable_mmu_icache_el1
Andrew Thoelke438c63a2014-04-28 12:06:18 +010023 .globl disable_mmu_icache_el3
Soby Mathew4e28c202018-10-14 08:09:22 +010024 .globl fixup_gdt_reloc
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010025#if SUPPORT_VFP
26 .globl enable_vfp
27#endif
28
Andrew Thoelke38bde412014-03-18 13:46:55 +000029func smc
Achin Gupta4f6ad662013-10-25 09:08:21 +010030 smc #0
Kévin Petita877c252015-03-24 14:03:57 +000031endfunc smc
Sandrine Bailleux65f546a2013-11-28 09:43:06 +000032
33/* -----------------------------------------------------------------------
Douglas Raillard21362a92016-12-02 13:51:54 +000034 * void zero_normalmem(void *mem, unsigned int length);
35 *
36 * Initialise a region in normal memory to 0. This functions complies with the
37 * AAPCS and can be called from C code.
38 *
39 * NOTE: MMU must be enabled when using this function as it can only operate on
40 * normal memory. It is intended to be mainly used from C code when MMU
41 * is usually enabled.
42 * -----------------------------------------------------------------------
43 */
44.equ zero_normalmem, zeromem_dczva
45
46/* -----------------------------------------------------------------------
47 * void zeromem(void *mem, unsigned int length);
48 *
49 * Initialise a region of device memory to 0. This functions complies with the
50 * AAPCS and can be called from C code.
51 *
52 * NOTE: When data caches and MMU are enabled, zero_normalmem can usually be
53 * used instead for faster zeroing.
54 *
55 * -----------------------------------------------------------------------
56 */
57func zeromem
58 /* x2 is the address past the last zeroed address */
59 add x2, x0, x1
60 /*
61 * Uses the fallback path that does not use DC ZVA instruction and
62 * therefore does not need enabled MMU
63 */
64 b .Lzeromem_dczva_fallback_entry
65endfunc zeromem
66
67/* -----------------------------------------------------------------------
68 * void zeromem_dczva(void *mem, unsigned int length);
69 *
70 * Fill a region of normal memory of size "length" in bytes with null bytes.
71 * MMU must be enabled and the memory be of
72 * normal type. This is because this function internally uses the DC ZVA
73 * instruction, which generates an Alignment fault if used on any type of
74 * Device memory (see section D3.4.9 of the ARMv8 ARM, issue k). When the MMU
75 * is disabled, all memory behaves like Device-nGnRnE memory (see section
76 * D4.2.8), hence the requirement on the MMU being enabled.
77 * NOTE: The code assumes that the block size as defined in DCZID_EL0
78 * register is at least 16 bytes.
79 *
80 * -----------------------------------------------------------------------
81 */
82func zeromem_dczva
83
84 /*
85 * The function consists of a series of loops that zero memory one byte
86 * at a time, 16 bytes at a time or using the DC ZVA instruction to
87 * zero aligned block of bytes, which is assumed to be more than 16.
88 * In the case where the DC ZVA instruction cannot be used or if the
89 * first 16 bytes loop would overflow, there is fallback path that does
90 * not use DC ZVA.
91 * Note: The fallback path is also used by the zeromem function that
92 * branches to it directly.
93 *
94 * +---------+ zeromem_dczva
95 * | entry |
96 * +----+----+
97 * |
98 * v
99 * +---------+
100 * | checks |>o-------+ (If any check fails, fallback)
101 * +----+----+ |
102 * | |---------------+
103 * v | Fallback path |
104 * +------+------+ |---------------+
105 * | 1 byte loop | |
106 * +------+------+ .Lzeromem_dczva_initial_1byte_aligned_end
107 * | |
108 * v |
109 * +-------+-------+ |
110 * | 16 bytes loop | |
111 * +-------+-------+ |
112 * | |
113 * v |
114 * +------+------+ .Lzeromem_dczva_blocksize_aligned
115 * | DC ZVA loop | |
116 * +------+------+ |
117 * +--------+ | |
118 * | | | |
119 * | v v |
120 * | +-------+-------+ .Lzeromem_dczva_final_16bytes_aligned
121 * | | 16 bytes loop | |
122 * | +-------+-------+ |
123 * | | |
124 * | v |
125 * | +------+------+ .Lzeromem_dczva_final_1byte_aligned
126 * | | 1 byte loop | |
127 * | +-------------+ |
128 * | | |
129 * | v |
130 * | +---+--+ |
131 * | | exit | |
132 * | +------+ |
133 * | |
134 * | +--------------+ +------------------+ zeromem
135 * | | +----------------| zeromem function |
136 * | | | +------------------+
137 * | v v
138 * | +-------------+ .Lzeromem_dczva_fallback_entry
139 * | | 1 byte loop |
140 * | +------+------+
141 * | |
142 * +-----------+
143 */
144
145 /*
146 * Readable names for registers
147 *
148 * Registers x0, x1 and x2 are also set by zeromem which
149 * branches into the fallback path directly, so cursor, length and
150 * stop_address should not be retargeted to other registers.
151 */
152 cursor .req x0 /* Start address and then current address */
153 length .req x1 /* Length in bytes of the region to zero out */
154 /* Reusing x1 as length is never used after block_mask is set */
155 block_mask .req x1 /* Bitmask of the block size read in DCZID_EL0 */
156 stop_address .req x2 /* Address past the last zeroed byte */
157 block_size .req x3 /* Size of a block in bytes as read in DCZID_EL0 */
158 tmp1 .req x4
159 tmp2 .req x5
160
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +0100161#if ENABLE_ASSERTIONS
Douglas Raillard21362a92016-12-02 13:51:54 +0000162 /*
163 * Check for M bit (MMU enabled) of the current SCTLR_EL(1|3)
164 * register value and panic if the MMU is disabled.
165 */
Zelalem Aweke688fbf72021-07-09 11:37:10 -0500166#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || (defined(IMAGE_BL2) && \
167 (BL2_AT_EL3 || ENABLE_RME))
Douglas Raillard21362a92016-12-02 13:51:54 +0000168 mrs tmp1, sctlr_el3
169#else
170 mrs tmp1, sctlr_el1
Soby Mathew041f62a2014-07-14 16:58:03 +0100171#endif
Douglas Raillard21362a92016-12-02 13:51:54 +0000172
173 tst tmp1, #SCTLR_M_BIT
174 ASM_ASSERT(ne)
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +0100175#endif /* ENABLE_ASSERTIONS */
Douglas Raillard21362a92016-12-02 13:51:54 +0000176
177 /* stop_address is the address past the last to zero */
178 add stop_address, cursor, length
179
180 /*
181 * Get block_size = (log2(<block size>) >> 2) (see encoding of
182 * dczid_el0 reg)
183 */
184 mrs block_size, dczid_el0
185
186 /*
187 * Select the 4 lowest bits and convert the extracted log2(<block size
188 * in words>) to <block size in bytes>
189 */
190 ubfx block_size, block_size, #0, #4
191 mov tmp2, #(1 << 2)
192 lsl block_size, tmp2, block_size
193
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +0100194#if ENABLE_ASSERTIONS
Douglas Raillard21362a92016-12-02 13:51:54 +0000195 /*
196 * Assumes block size is at least 16 bytes to avoid manual realignment
197 * of the cursor at the end of the DCZVA loop.
198 */
199 cmp block_size, #16
200 ASM_ASSERT(hs)
201#endif
202 /*
203 * Not worth doing all the setup for a region less than a block and
204 * protects against zeroing a whole block when the area to zero is
205 * smaller than that. Also, as it is assumed that the block size is at
206 * least 16 bytes, this also protects the initial aligning loops from
207 * trying to zero 16 bytes when length is less than 16.
208 */
209 cmp length, block_size
210 b.lo .Lzeromem_dczva_fallback_entry
211
212 /*
213 * Calculate the bitmask of the block alignment. It will never
214 * underflow as the block size is between 4 bytes and 2kB.
215 * block_mask = block_size - 1
216 */
217 sub block_mask, block_size, #1
218
219 /*
220 * length alias should not be used after this point unless it is
221 * defined as a register other than block_mask's.
222 */
223 .unreq length
224
225 /*
226 * If the start address is already aligned to zero block size, go
227 * straight to the cache zeroing loop. This is safe because at this
228 * point, the length cannot be smaller than a block size.
229 */
230 tst cursor, block_mask
231 b.eq .Lzeromem_dczva_blocksize_aligned
232
233 /*
234 * Calculate the first block-size-aligned address. It is assumed that
235 * the zero block size is at least 16 bytes. This address is the last
236 * address of this initial loop.
237 */
238 orr tmp1, cursor, block_mask
239 add tmp1, tmp1, #1
240
241 /*
242 * If the addition overflows, skip the cache zeroing loops. This is
243 * quite unlikely however.
244 */
245 cbz tmp1, .Lzeromem_dczva_fallback_entry
246
247 /*
248 * If the first block-size-aligned address is past the last address,
249 * fallback to the simpler code.
250 */
251 cmp tmp1, stop_address
252 b.hi .Lzeromem_dczva_fallback_entry
253
254 /*
255 * If the start address is already aligned to 16 bytes, skip this loop.
256 * It is safe to do this because tmp1 (the stop address of the initial
257 * 16 bytes loop) will never be greater than the final stop address.
258 */
259 tst cursor, #0xf
260 b.eq .Lzeromem_dczva_initial_1byte_aligned_end
261
262 /* Calculate the next address aligned to 16 bytes */
263 orr tmp2, cursor, #0xf
264 add tmp2, tmp2, #1
265 /* If it overflows, fallback to the simple path (unlikely) */
266 cbz tmp2, .Lzeromem_dczva_fallback_entry
267 /*
268 * Next aligned address cannot be after the stop address because the
269 * length cannot be smaller than 16 at this point.
270 */
271
272 /* First loop: zero byte per byte */
2731:
274 strb wzr, [cursor], #1
275 cmp cursor, tmp2
276 b.ne 1b
277.Lzeromem_dczva_initial_1byte_aligned_end:
278
279 /*
280 * Second loop: we need to zero 16 bytes at a time from cursor to tmp1
281 * before being able to use the code that deals with block-size-aligned
282 * addresses.
283 */
284 cmp cursor, tmp1
285 b.hs 2f
2861:
287 stp xzr, xzr, [cursor], #16
288 cmp cursor, tmp1
289 b.lo 1b
2902:
291
292 /*
293 * Third loop: zero a block at a time using DC ZVA cache block zeroing
294 * instruction.
295 */
296.Lzeromem_dczva_blocksize_aligned:
297 /*
298 * Calculate the last block-size-aligned address. If the result equals
299 * to the start address, the loop will exit immediately.
300 */
301 bic tmp1, stop_address, block_mask
302
303 cmp cursor, tmp1
304 b.hs 2f
3051:
306 /* Zero the block containing the cursor */
307 dc zva, cursor
308 /* Increment the cursor by the size of a block */
309 add cursor, cursor, block_size
310 cmp cursor, tmp1
311 b.lo 1b
3122:
313
314 /*
315 * Fourth loop: zero 16 bytes at a time and then byte per byte the
316 * remaining area
317 */
318.Lzeromem_dczva_final_16bytes_aligned:
319 /*
320 * Calculate the last 16 bytes aligned address. It is assumed that the
321 * block size will never be smaller than 16 bytes so that the current
322 * cursor is aligned to at least 16 bytes boundary.
323 */
324 bic tmp1, stop_address, #15
325
326 cmp cursor, tmp1
327 b.hs 2f
3281:
329 stp xzr, xzr, [cursor], #16
330 cmp cursor, tmp1
331 b.lo 1b
3322:
333
334 /* Fifth and final loop: zero byte per byte */
335.Lzeromem_dczva_final_1byte_aligned:
336 cmp cursor, stop_address
337 b.eq 2f
3381:
339 strb wzr, [cursor], #1
340 cmp cursor, stop_address
341 b.ne 1b
3422:
Kévin Petita877c252015-03-24 14:03:57 +0000343 ret
Douglas Raillard21362a92016-12-02 13:51:54 +0000344
345 /* Fallback for unaligned start addresses */
346.Lzeromem_dczva_fallback_entry:
347 /*
348 * If the start address is already aligned to 16 bytes, skip this loop.
349 */
350 tst cursor, #0xf
351 b.eq .Lzeromem_dczva_final_16bytes_aligned
352
353 /* Calculate the next address aligned to 16 bytes */
354 orr tmp1, cursor, #15
355 add tmp1, tmp1, #1
356 /* If it overflows, fallback to byte per byte zeroing */
357 cbz tmp1, .Lzeromem_dczva_final_1byte_aligned
358 /* If the next aligned address is after the stop address, fall back */
359 cmp tmp1, stop_address
360 b.hs .Lzeromem_dczva_final_1byte_aligned
361
362 /* Fallback entry loop: zero byte per byte */
3631:
364 strb wzr, [cursor], #1
365 cmp cursor, tmp1
366 b.ne 1b
367
368 b .Lzeromem_dczva_final_16bytes_aligned
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000369
Douglas Raillard21362a92016-12-02 13:51:54 +0000370 .unreq cursor
371 /*
372 * length is already unreq'ed to reuse the register for another
373 * variable.
374 */
375 .unreq stop_address
376 .unreq block_size
377 .unreq block_mask
378 .unreq tmp1
379 .unreq tmp2
380endfunc zeromem_dczva
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000381
382/* --------------------------------------------------------------------------
383 * void memcpy16(void *dest, const void *src, unsigned int length)
384 *
385 * Copy length bytes from memory area src to memory area dest.
386 * The memory areas should not overlap.
387 * Destination and source addresses must be 16-byte aligned.
388 * --------------------------------------------------------------------------
389 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000390func memcpy16
Antonio Nino Diaz7c65c1e2017-04-20 09:58:28 +0100391#if ENABLE_ASSERTIONS
Soby Mathew041f62a2014-07-14 16:58:03 +0100392 orr x3, x0, x1
393 tst x3, #0xf
394 ASM_ASSERT(eq)
395#endif
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000396/* copy 16 bytes at a time */
397m_loop16:
398 cmp x2, #16
Douglas Raillard861be8e2016-12-02 13:56:06 +0000399 b.lo m_loop1
Sandrine Bailleux65f546a2013-11-28 09:43:06 +0000400 ldp x3, x4, [x1], #16
401 stp x3, x4, [x0], #16
402 sub x2, x2, #16
403 b m_loop16
404/* copy byte per byte */
405m_loop1:
406 cbz x2, m_end
407 ldrb w3, [x1], #1
408 strb w3, [x0], #1
409 subs x2, x2, #1
410 b.ne m_loop1
Kévin Petita877c252015-03-24 14:03:57 +0000411m_end:
412 ret
413endfunc memcpy16
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100414
415/* ---------------------------------------------------------------------------
416 * Disable the MMU at EL3
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100417 * ---------------------------------------------------------------------------
418 */
419
420func disable_mmu_el3
421 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100422do_disable_mmu_el3:
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100423 mrs x0, sctlr_el3
424 bic x0, x0, x1
425 msr sctlr_el3, x0
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100426 isb /* ensure MMU is off */
Achin Guptae9c4a642015-09-11 16:03:13 +0100427 dsb sy
428 ret
Kévin Petita877c252015-03-24 14:03:57 +0000429endfunc disable_mmu_el3
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100430
431
432func disable_mmu_icache_el3
433 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100434 b do_disable_mmu_el3
Kévin Petita877c252015-03-24 14:03:57 +0000435endfunc disable_mmu_icache_el3
Andrew Thoelke438c63a2014-04-28 12:06:18 +0100436
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100437/* ---------------------------------------------------------------------------
Antonio Nino Diaz4613d5f2017-10-05 15:19:42 +0100438 * Disable the MMU at EL1
439 * ---------------------------------------------------------------------------
440 */
441
442func disable_mmu_el1
443 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT)
444do_disable_mmu_el1:
445 mrs x0, sctlr_el1
446 bic x0, x0, x1
447 msr sctlr_el1, x0
448 isb /* ensure MMU is off */
449 dsb sy
450 ret
451endfunc disable_mmu_el1
452
453
454func disable_mmu_icache_el1
455 mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
456 b do_disable_mmu_el1
457endfunc disable_mmu_icache_el1
458
459/* ---------------------------------------------------------------------------
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100460 * Enable the use of VFP at EL3
461 * ---------------------------------------------------------------------------
462 */
463#if SUPPORT_VFP
464func enable_vfp
465 mrs x0, cpacr_el1
466 orr x0, x0, #CPACR_VFP_BITS
467 msr cpacr_el1, x0
468 mrs x0, cptr_el3
469 mov x1, #AARCH64_CPTR_TFP
470 bic x0, x0, x1
471 msr cptr_el3, x0
472 isb
473 ret
Kévin Petita877c252015-03-24 14:03:57 +0000474endfunc enable_vfp
Andrew Thoelke3f78dc32014-06-02 15:44:43 +0100475#endif
Soby Mathew4e28c202018-10-14 08:09:22 +0100476
477/* ---------------------------------------------------------------------------
478 * Helper to fixup Global Descriptor table (GDT) and dynamic relocations
479 * (.rela.dyn) at runtime.
480 *
481 * This function is meant to be used when the firmware is compiled with -fpie
482 * and linked with -pie options. We rely on the linker script exporting
483 * appropriate markers for start and end of the section. For GOT, we
484 * expect __GOT_START__ and __GOT_END__. Similarly for .rela.dyn, we expect
485 * __RELA_START__ and __RELA_END__.
486 *
487 * The function takes the limits of the memory to apply fixups to as
488 * arguments (which is usually the limits of the relocable BL image).
489 * x0 - the start of the fixup region
490 * x1 - the limit of the fixup region
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000491 * These addresses have to be 4KB page aligned.
Soby Mathew4e28c202018-10-14 08:09:22 +0100492 * ---------------------------------------------------------------------------
493 */
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000494
495/* Relocation codes */
496#define R_AARCH64_NONE 0
497#define R_AARCH64_RELATIVE 1027
498
Soby Mathew4e28c202018-10-14 08:09:22 +0100499func fixup_gdt_reloc
500 mov x6, x0
501 mov x7, x1
502
Soby Mathew4e28c202018-10-14 08:09:22 +0100503#if ENABLE_ASSERTIONS
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000504 /* Test if the limits are 4KB aligned */
Soby Mathew4e28c202018-10-14 08:09:22 +0100505 orr x0, x0, x1
Jimmy Brissoned202072020-08-04 16:18:52 -0500506 tst x0, #(PAGE_SIZE_MASK)
Soby Mathew4e28c202018-10-14 08:09:22 +0100507 ASM_ASSERT(eq)
508#endif
509 /*
510 * Calculate the offset based on return address in x30.
Louis Mayencourt462ec472019-03-01 14:36:46 +0000511 * Assume that this function is called within a page at the start of
512 * fixup region.
Soby Mathew4e28c202018-10-14 08:09:22 +0100513 */
Jimmy Brissoned202072020-08-04 16:18:52 -0500514 and x2, x30, #~(PAGE_SIZE_MASK)
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000515 subs x0, x2, x6 /* Diff(S) = Current Address - Compiled Address */
516 b.eq 3f /* Diff(S) = 0. No relocation needed */
Soby Mathew4e28c202018-10-14 08:09:22 +0100517
518 adrp x1, __GOT_START__
519 add x1, x1, :lo12:__GOT_START__
520 adrp x2, __GOT_END__
521 add x2, x2, :lo12:__GOT_END__
522
523 /*
524 * GOT is an array of 64_bit addresses which must be fixed up as
525 * new_addr = old_addr + Diff(S).
526 * The new_addr is the address currently the binary is executing from
527 * and old_addr is the address at compile time.
528 */
Alexei Fedorovc69b7a92020-12-25 10:52:56 +00005291: ldr x3, [x1]
530
Soby Mathew4e28c202018-10-14 08:09:22 +0100531 /* Skip adding offset if address is < lower limit */
532 cmp x3, x6
533 b.lo 2f
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000534
Yann Gautier8c25dc72021-10-27 17:16:09 +0200535 /* Skip adding offset if address is > upper limit */
Soby Mathew4e28c202018-10-14 08:09:22 +0100536 cmp x3, x7
Yann Gautier8c25dc72021-10-27 17:16:09 +0200537 b.hi 2f
Soby Mathew4e28c202018-10-14 08:09:22 +0100538 add x3, x3, x0
539 str x3, [x1]
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000540
5412: add x1, x1, #8
Soby Mathew4e28c202018-10-14 08:09:22 +0100542 cmp x1, x2
543 b.lo 1b
544
545 /* Starting dynamic relocations. Use adrp/adr to get RELA_START and END */
Alexei Fedorovc69b7a92020-12-25 10:52:56 +00005463: adrp x1, __RELA_START__
Soby Mathew4e28c202018-10-14 08:09:22 +0100547 add x1, x1, :lo12:__RELA_START__
548 adrp x2, __RELA_END__
549 add x2, x2, :lo12:__RELA_END__
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000550
Soby Mathew4e28c202018-10-14 08:09:22 +0100551 /*
552 * According to ELF-64 specification, the RELA data structure is as
553 * follows:
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000554 * typedef struct {
Soby Mathew4e28c202018-10-14 08:09:22 +0100555 * Elf64_Addr r_offset;
556 * Elf64_Xword r_info;
557 * Elf64_Sxword r_addend;
558 * } Elf64_Rela;
559 *
560 * r_offset is address of reference
561 * r_info is symbol index and type of relocation (in this case
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000562 * code 1027 which corresponds to R_AARCH64_RELATIVE).
Soby Mathew4e28c202018-10-14 08:09:22 +0100563 * r_addend is constant part of expression.
564 *
565 * Size of Elf64_Rela structure is 24 bytes.
566 */
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000567
568 /* Skip R_AARCH64_NONE entry with code 0 */
5691: ldr x3, [x1, #8]
570 cbz x3, 2f
571
Soby Mathew4e28c202018-10-14 08:09:22 +0100572#if ENABLE_ASSERTIONS
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000573 /* Assert that the relocation type is R_AARCH64_RELATIVE */
574 cmp x3, #R_AARCH64_RELATIVE
Soby Mathew4e28c202018-10-14 08:09:22 +0100575 ASM_ASSERT(eq)
576#endif
577 ldr x3, [x1] /* r_offset */
578 add x3, x0, x3
579 ldr x4, [x1, #16] /* r_addend */
580
581 /* Skip adding offset if r_addend is < lower limit */
582 cmp x4, x6
583 b.lo 2f
Alexei Fedorovc69b7a92020-12-25 10:52:56 +0000584
Yann Gautier8c25dc72021-10-27 17:16:09 +0200585 /* Skip adding offset if r_addend entry is > upper limit */
Soby Mathew4e28c202018-10-14 08:09:22 +0100586 cmp x4, x7
Yann Gautier8c25dc72021-10-27 17:16:09 +0200587 b.hi 2f
Soby Mathew4e28c202018-10-14 08:09:22 +0100588
589 add x4, x0, x4 /* Diff(S) + r_addend */
590 str x4, [x3]
591
5922: add x1, x1, #24
593 cmp x1, x2
594 b.lo 1b
Soby Mathew4e28c202018-10-14 08:09:22 +0100595 ret
596endfunc fixup_gdt_reloc
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500597
598/*
599 * TODO: Currently only supports size of 4KB,
600 * support other sizes as well.
601 */
Robert Wakim48e6b572021-10-21 15:39:56 +0100602func gpt_tlbi_by_pa_ll
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500603#if ENABLE_ASSERTIONS
604 cmp x1, #PAGE_SIZE_4KB
605 ASM_ASSERT(eq)
606 tst x0, #(PAGE_SIZE_MASK)
607 ASM_ASSERT(eq)
608#endif
609 lsr x0, x0, #FOUR_KB_SHIFT /* 4KB size encoding is zero */
Robert Wakim48e6b572021-10-21 15:39:56 +0100610 sys #6, c8, c4, #7, x0 /* TLBI RPALOS, <Xt> */
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500611 dsb sy
612 ret
Robert Wakim48e6b572021-10-21 15:39:56 +0100613endfunc gpt_tlbi_by_pa_ll