Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 31 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 32 | #include <asm_macros.S> |
Achin Gupta | 4a826dd | 2013-11-25 14:00:56 +0000 | [diff] [blame] | 33 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | .globl enable_irq |
| 35 | .globl disable_irq |
| 36 | |
| 37 | .globl enable_fiq |
| 38 | .globl disable_fiq |
| 39 | |
| 40 | .globl enable_serror |
| 41 | .globl disable_serror |
| 42 | |
Sandrine Bailleux | 3738274 | 2013-11-18 17:26:59 +0000 | [diff] [blame] | 43 | .globl enable_debug_exceptions |
| 44 | .globl disable_debug_exceptions |
| 45 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 46 | .globl read_daif |
| 47 | .globl write_daif |
| 48 | |
| 49 | .globl read_spsr |
| 50 | .globl read_spsr_el1 |
| 51 | .globl read_spsr_el2 |
| 52 | .globl read_spsr_el3 |
| 53 | |
| 54 | .globl write_spsr |
| 55 | .globl write_spsr_el1 |
| 56 | .globl write_spsr_el2 |
| 57 | .globl write_spsr_el3 |
| 58 | |
| 59 | .globl read_elr |
| 60 | .globl read_elr_el1 |
| 61 | .globl read_elr_el2 |
| 62 | .globl read_elr_el3 |
| 63 | |
| 64 | .globl write_elr |
| 65 | .globl write_elr_el1 |
| 66 | .globl write_elr_el2 |
| 67 | .globl write_elr_el3 |
| 68 | |
| 69 | .globl get_afflvl_shift |
| 70 | .globl mpidr_mask_lower_afflvls |
| 71 | .globl dsb |
| 72 | .globl isb |
| 73 | .globl sev |
| 74 | .globl wfe |
| 75 | .globl wfi |
| 76 | .globl eret |
| 77 | .globl smc |
| 78 | |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 79 | .globl zeromem16 |
| 80 | .globl memcpy16 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 81 | |
Andrew Thoelke | 438c63a | 2014-04-28 12:06:18 +0100 | [diff] [blame^] | 82 | .globl disable_mmu_el3 |
| 83 | .globl disable_mmu_icache_el3 |
| 84 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 85 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 86 | func get_afflvl_shift |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 87 | cmp x0, #3 |
| 88 | cinc x0, x0, eq |
| 89 | mov x1, #MPIDR_AFFLVL_SHIFT |
| 90 | lsl x0, x0, x1 |
| 91 | ret |
| 92 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 93 | func mpidr_mask_lower_afflvls |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 94 | cmp x1, #3 |
| 95 | cinc x1, x1, eq |
| 96 | mov x2, #MPIDR_AFFLVL_SHIFT |
| 97 | lsl x2, x1, x2 |
| 98 | lsr x0, x0, x2 |
| 99 | lsl x0, x0, x2 |
| 100 | ret |
| 101 | |
| 102 | /* ----------------------------------------------------- |
| 103 | * Asynchronous exception manipulation accessors |
| 104 | * ----------------------------------------------------- |
| 105 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 106 | func enable_irq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 107 | msr daifclr, #DAIF_IRQ_BIT |
| 108 | ret |
| 109 | |
| 110 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 111 | func enable_fiq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 112 | msr daifclr, #DAIF_FIQ_BIT |
| 113 | ret |
| 114 | |
| 115 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 116 | func enable_serror |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 117 | msr daifclr, #DAIF_ABT_BIT |
| 118 | ret |
| 119 | |
| 120 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 121 | func enable_debug_exceptions |
Sandrine Bailleux | 3738274 | 2013-11-18 17:26:59 +0000 | [diff] [blame] | 122 | msr daifclr, #DAIF_DBG_BIT |
| 123 | ret |
| 124 | |
| 125 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 126 | func disable_irq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 127 | msr daifset, #DAIF_IRQ_BIT |
| 128 | ret |
| 129 | |
| 130 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 131 | func disable_fiq |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 132 | msr daifset, #DAIF_FIQ_BIT |
| 133 | ret |
| 134 | |
| 135 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 136 | func disable_serror |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 137 | msr daifset, #DAIF_ABT_BIT |
| 138 | ret |
| 139 | |
| 140 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 141 | func disable_debug_exceptions |
Sandrine Bailleux | 3738274 | 2013-11-18 17:26:59 +0000 | [diff] [blame] | 142 | msr daifset, #DAIF_DBG_BIT |
| 143 | ret |
| 144 | |
| 145 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 146 | func read_daif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 147 | mrs x0, daif |
| 148 | ret |
| 149 | |
| 150 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 151 | func write_daif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 152 | msr daif, x0 |
| 153 | ret |
| 154 | |
| 155 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 156 | func read_spsr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 157 | mrs x0, CurrentEl |
| 158 | cmp x0, #(MODE_EL1 << MODE_EL_SHIFT) |
| 159 | b.eq read_spsr_el1 |
| 160 | cmp x0, #(MODE_EL2 << MODE_EL_SHIFT) |
| 161 | b.eq read_spsr_el2 |
| 162 | cmp x0, #(MODE_EL3 << MODE_EL_SHIFT) |
| 163 | b.eq read_spsr_el3 |
| 164 | |
| 165 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 166 | func read_spsr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 167 | mrs x0, spsr_el1 |
| 168 | ret |
| 169 | |
| 170 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 171 | func read_spsr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 172 | mrs x0, spsr_el2 |
| 173 | ret |
| 174 | |
| 175 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 176 | func read_spsr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 177 | mrs x0, spsr_el3 |
| 178 | ret |
| 179 | |
| 180 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 181 | func write_spsr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 182 | mrs x1, CurrentEl |
| 183 | cmp x1, #(MODE_EL1 << MODE_EL_SHIFT) |
| 184 | b.eq write_spsr_el1 |
| 185 | cmp x1, #(MODE_EL2 << MODE_EL_SHIFT) |
| 186 | b.eq write_spsr_el2 |
| 187 | cmp x1, #(MODE_EL3 << MODE_EL_SHIFT) |
| 188 | b.eq write_spsr_el3 |
| 189 | |
| 190 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 191 | func write_spsr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 192 | msr spsr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 193 | ret |
| 194 | |
| 195 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 196 | func write_spsr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 197 | msr spsr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 198 | ret |
| 199 | |
| 200 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 201 | func write_spsr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 202 | msr spsr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 203 | ret |
| 204 | |
| 205 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 206 | func read_elr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 207 | mrs x0, CurrentEl |
| 208 | cmp x0, #(MODE_EL1 << MODE_EL_SHIFT) |
| 209 | b.eq read_elr_el1 |
| 210 | cmp x0, #(MODE_EL2 << MODE_EL_SHIFT) |
| 211 | b.eq read_elr_el2 |
| 212 | cmp x0, #(MODE_EL3 << MODE_EL_SHIFT) |
| 213 | b.eq read_elr_el3 |
| 214 | |
| 215 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 216 | func read_elr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 217 | mrs x0, elr_el1 |
| 218 | ret |
| 219 | |
| 220 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 221 | func read_elr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 222 | mrs x0, elr_el2 |
| 223 | ret |
| 224 | |
| 225 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 226 | func read_elr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 227 | mrs x0, elr_el3 |
| 228 | ret |
| 229 | |
| 230 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 231 | func write_elr |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 232 | mrs x1, CurrentEl |
| 233 | cmp x1, #(MODE_EL1 << MODE_EL_SHIFT) |
| 234 | b.eq write_elr_el1 |
| 235 | cmp x1, #(MODE_EL2 << MODE_EL_SHIFT) |
| 236 | b.eq write_elr_el2 |
| 237 | cmp x1, #(MODE_EL3 << MODE_EL_SHIFT) |
| 238 | b.eq write_elr_el3 |
| 239 | |
| 240 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 241 | func write_elr_el1 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 242 | msr elr_el1, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 243 | ret |
| 244 | |
| 245 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 246 | func write_elr_el2 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 247 | msr elr_el2, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 248 | ret |
| 249 | |
| 250 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 251 | func write_elr_el3 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 252 | msr elr_el3, x0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 253 | ret |
| 254 | |
| 255 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 256 | func dsb |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 257 | dsb sy |
| 258 | ret |
| 259 | |
| 260 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 261 | func isb |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 262 | isb |
| 263 | ret |
| 264 | |
| 265 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 266 | func sev |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 267 | sev |
| 268 | ret |
| 269 | |
| 270 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 271 | func wfe |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 272 | wfe |
| 273 | ret |
| 274 | |
| 275 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 276 | func wfi |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 277 | wfi |
| 278 | ret |
| 279 | |
| 280 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 281 | func eret |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 282 | eret |
| 283 | |
| 284 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 285 | func smc |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 286 | smc #0 |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 287 | |
| 288 | /* ----------------------------------------------------------------------- |
| 289 | * void zeromem16(void *mem, unsigned int length); |
| 290 | * |
| 291 | * Initialise a memory region to 0. |
| 292 | * The memory address must be 16-byte aligned. |
| 293 | * ----------------------------------------------------------------------- |
| 294 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 295 | func zeromem16 |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 296 | add x2, x0, x1 |
| 297 | /* zero 16 bytes at a time */ |
| 298 | z_loop16: |
| 299 | sub x3, x2, x0 |
| 300 | cmp x3, #16 |
| 301 | b.lt z_loop1 |
| 302 | stp xzr, xzr, [x0], #16 |
| 303 | b z_loop16 |
| 304 | /* zero byte per byte */ |
| 305 | z_loop1: |
| 306 | cmp x0, x2 |
| 307 | b.eq z_end |
| 308 | strb wzr, [x0], #1 |
| 309 | b z_loop1 |
| 310 | z_end: ret |
| 311 | |
| 312 | |
| 313 | /* -------------------------------------------------------------------------- |
| 314 | * void memcpy16(void *dest, const void *src, unsigned int length) |
| 315 | * |
| 316 | * Copy length bytes from memory area src to memory area dest. |
| 317 | * The memory areas should not overlap. |
| 318 | * Destination and source addresses must be 16-byte aligned. |
| 319 | * -------------------------------------------------------------------------- |
| 320 | */ |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 321 | func memcpy16 |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 322 | /* copy 16 bytes at a time */ |
| 323 | m_loop16: |
| 324 | cmp x2, #16 |
| 325 | b.lt m_loop1 |
| 326 | ldp x3, x4, [x1], #16 |
| 327 | stp x3, x4, [x0], #16 |
| 328 | sub x2, x2, #16 |
| 329 | b m_loop16 |
| 330 | /* copy byte per byte */ |
| 331 | m_loop1: |
| 332 | cbz x2, m_end |
| 333 | ldrb w3, [x1], #1 |
| 334 | strb w3, [x0], #1 |
| 335 | subs x2, x2, #1 |
| 336 | b.ne m_loop1 |
| 337 | m_end: ret |
Andrew Thoelke | 438c63a | 2014-04-28 12:06:18 +0100 | [diff] [blame^] | 338 | |
| 339 | /* --------------------------------------------------------------------------- |
| 340 | * Disable the MMU at EL3 |
| 341 | * This is implemented in assembler to ensure that the data cache is cleaned |
| 342 | * and invalidated after the MMU is disabled without any intervening cacheable |
| 343 | * data accesses |
| 344 | * --------------------------------------------------------------------------- |
| 345 | */ |
| 346 | |
| 347 | func disable_mmu_el3 |
| 348 | mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT) |
| 349 | do_disable_mmu: |
| 350 | mrs x0, sctlr_el3 |
| 351 | bic x0, x0, x1 |
| 352 | msr sctlr_el3, x0 |
| 353 | isb // ensure MMU is off |
| 354 | mov x0, #DCCISW // DCache clean and invalidate |
| 355 | b dcsw_op_all |
| 356 | |
| 357 | |
| 358 | func disable_mmu_icache_el3 |
| 359 | mov x1, #(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT) |
| 360 | b do_disable_mmu |
| 361 | |