blob: df943969e2b7f14278afdfd1e819018af4092368 [file] [log] [blame]
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +05301/*
Krishna Reddyae18d222017-12-07 13:52:39 -08002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +05303 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +05305 */
6
Puneet Saxenacf8c0e22017-08-04 17:19:55 +05307#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008#include <common/bl_common.h>
9
Steven Kaoa457f2e2017-11-14 18:52:05 +080010#include <mce.h>
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053011#include <memctrl_v2.h>
Puneet Saxenacf8c0e22017-08-04 17:19:55 +053012#include <tegra_mc_def.h>
13#include <tegra_platform.h>
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053014
15/*******************************************************************************
16 * Array to hold stream_id override config register offsets
17 ******************************************************************************/
18const static uint32_t tegra186_streamid_override_regs[] = {
19 MC_STREAMID_OVERRIDE_CFG_PTCR,
20 MC_STREAMID_OVERRIDE_CFG_AFIR,
21 MC_STREAMID_OVERRIDE_CFG_HDAR,
22 MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
23 MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
24 MC_STREAMID_OVERRIDE_CFG_SATAR,
25 MC_STREAMID_OVERRIDE_CFG_MPCORER,
26 MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
27 MC_STREAMID_OVERRIDE_CFG_AFIW,
28 MC_STREAMID_OVERRIDE_CFG_HDAW,
29 MC_STREAMID_OVERRIDE_CFG_MPCOREW,
30 MC_STREAMID_OVERRIDE_CFG_SATAW,
31 MC_STREAMID_OVERRIDE_CFG_ISPRA,
32 MC_STREAMID_OVERRIDE_CFG_ISPWA,
33 MC_STREAMID_OVERRIDE_CFG_ISPWB,
34 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
35 MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
36 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
37 MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
38 MC_STREAMID_OVERRIDE_CFG_TSECSRD,
39 MC_STREAMID_OVERRIDE_CFG_TSECSWR,
40 MC_STREAMID_OVERRIDE_CFG_GPUSRD,
41 MC_STREAMID_OVERRIDE_CFG_GPUSWR,
42 MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
43 MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
44 MC_STREAMID_OVERRIDE_CFG_SDMMCR,
45 MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
46 MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
47 MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
48 MC_STREAMID_OVERRIDE_CFG_SDMMCW,
49 MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
50 MC_STREAMID_OVERRIDE_CFG_VICSRD,
51 MC_STREAMID_OVERRIDE_CFG_VICSWR,
52 MC_STREAMID_OVERRIDE_CFG_VIW,
53 MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
54 MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
55 MC_STREAMID_OVERRIDE_CFG_APER,
56 MC_STREAMID_OVERRIDE_CFG_APEW,
57 MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
58 MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
59 MC_STREAMID_OVERRIDE_CFG_SESRD,
60 MC_STREAMID_OVERRIDE_CFG_SESWR,
61 MC_STREAMID_OVERRIDE_CFG_ETRR,
62 MC_STREAMID_OVERRIDE_CFG_ETRW,
63 MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
64 MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
65 MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
66 MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
67 MC_STREAMID_OVERRIDE_CFG_AXISR,
68 MC_STREAMID_OVERRIDE_CFG_AXISW,
69 MC_STREAMID_OVERRIDE_CFG_EQOSR,
70 MC_STREAMID_OVERRIDE_CFG_EQOSW,
71 MC_STREAMID_OVERRIDE_CFG_UFSHCR,
72 MC_STREAMID_OVERRIDE_CFG_UFSHCW,
73 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
74 MC_STREAMID_OVERRIDE_CFG_BPMPR,
75 MC_STREAMID_OVERRIDE_CFG_BPMPW,
76 MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
77 MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
78 MC_STREAMID_OVERRIDE_CFG_AONR,
79 MC_STREAMID_OVERRIDE_CFG_AONW,
80 MC_STREAMID_OVERRIDE_CFG_AONDMAR,
81 MC_STREAMID_OVERRIDE_CFG_AONDMAW,
82 MC_STREAMID_OVERRIDE_CFG_SCER,
83 MC_STREAMID_OVERRIDE_CFG_SCEW,
84 MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
85 MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
86 MC_STREAMID_OVERRIDE_CFG_APEDMAR,
87 MC_STREAMID_OVERRIDE_CFG_APEDMAW,
88 MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
89 MC_STREAMID_OVERRIDE_CFG_VICSRD1,
90 MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
91};
92
93/*******************************************************************************
94 * Array to hold the security configs for stream IDs
95 ******************************************************************************/
96const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
Krishna Reddyae18d222017-12-07 13:52:39 -080097 mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +053098 mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
99 mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
100 mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
101 mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
102 mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
103 mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
104 mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
105 mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
106 mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
107 mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
108 mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
109 mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
110 mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
111 mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800112 mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530113 mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
114 mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
115 mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
116 mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
117 mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800118 mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530119 mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
120 mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
121 mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800122 mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530123 mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
124 mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
125 mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
126 mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
127 mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
128 mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE),
129 mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
130 mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
131 mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800132 mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530133 mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
134 mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
135 mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800136 mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530137 mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
138 mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800139 mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530140 mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800141 mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530142 mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
143 mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
144 mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800145 mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530146 mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
147 mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
148 mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
149 mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
150 mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
151 mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
152 mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
153 mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800154 mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530155 mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
156 mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
157 mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
158 mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
159 mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
160 mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
161 mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
162 mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
163 mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
164 mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
Krishna Reddyae18d222017-12-07 13:52:39 -0800165 mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
166 mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
167 mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
168 mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530169};
170
171/*******************************************************************************
172 * Array to hold the transaction override configs
173 ******************************************************************************/
174const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
175 mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
176 mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
177 mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
178 mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
179 mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
180 mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
181 mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
182 mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
183 mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
184 mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
185 mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
186 mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
187 mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
188 mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
189 mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
190 mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
191 mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
192 mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
193 mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
194 mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
195 mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
196 mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
197 mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
198 mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
199 mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
200 mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
201 mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
202 mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
203 mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
204 mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
205 mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
206};
207
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530208static void tegra186_memctrl_reconfig_mss_clients(void)
209{
210#if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
211 uint32_t val, wdata_0, wdata_1;
212
213 /*
214 * Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for
215 * boot and strongly ordered MSS clients to flush existing memory
216 * traffic and stall future requests.
217 */
218 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
219 assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
220
221 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530222 MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530223 MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
224 MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
225 MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
226 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
227
228 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
229 do {
230 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
231 } while ((val & wdata_0) != wdata_0);
232
233 /* Wait one more time due to SW WAR for known legacy issue */
234 do {
235 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
236 } while ((val & wdata_0) != wdata_0);
237
238 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
239 assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL);
240
241 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
242 MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
243 MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
244 MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
245 MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
246 MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
247 MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
248 MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
249 MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
250 MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB;
251 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
252
253 /* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
254 do {
255 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
256 } while ((val & wdata_1) != wdata_1);
257
258 /* Wait one more time due to SW WAR for known legacy issue */
259 do {
260 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
261 } while ((val & wdata_1) != wdata_1);
262
263 /*
264 * Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
265 * strongly ordered MSS clients. ROC needs to be single point
266 * of control on overriding the memory type. So, remove TSA's
267 * memtype override.
268 *
269 * MC clients with default SO_DEV override still enabled at TSA:
270 * AONW, BPMPW, SCEW, APEW
271 */
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530272 mc_set_tsa_passthrough(AFIW);
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530273 mc_set_tsa_passthrough(HDAW);
274 mc_set_tsa_passthrough(SATAW);
275 mc_set_tsa_passthrough(XUSB_HOSTW);
276 mc_set_tsa_passthrough(XUSB_DEVW);
277 mc_set_tsa_passthrough(SDMMCWAB);
278 mc_set_tsa_passthrough(APEDMAW);
279 mc_set_tsa_passthrough(SESWR);
280 mc_set_tsa_passthrough(ETRW);
281 mc_set_tsa_passthrough(AXISW);
282 mc_set_tsa_passthrough(EQOSW);
283 mc_set_tsa_passthrough(UFSHCW);
284 mc_set_tsa_passthrough(BPMPDMAW);
285 mc_set_tsa_passthrough(AONDMAW);
286 mc_set_tsa_passthrough(SCEDMAW);
287
288 /* Parker has no IO Coherency support and need the following:
289 * Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB.
290 * ISO clients(DISP, VI, EQOS) should never snoop caches and
291 * don't need ROC/PCFIFO ordering.
292 * ISO clients(EQOS) that need ordering should use PCFIFO ordering
293 * and bypass ROC ordering by using FORCE_NON_COHERENT path.
294 * FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
295 * over SMMU attributes.
296 * Force all Normal memory transactions from ISO and non-ISO to be
297 * non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
298 * Force the SO_DEV transactions from ordered ISO clients(EQOS) to
299 * non-coherent path and enable MC PCFIFO interlock for ordering.
300 * Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
301 * XUSB, SATA) to coherent so that the transactions are
302 * ordered by ROC.
303 * PCFIFO ensure write ordering.
304 * Read after Write ordering is maintained/enforced by MC clients.
305 * Clients that need PCIe type write ordering must
306 * go through ROC ordering.
307 * Ordering enable for Read clients is not necessary.
308 * R5's and A9 would get necessary ordering from AXI and
309 * don't need ROC ordering enable:
310 * - MMIO ordering is through dev mapping and MMIO
311 * accesses bypass SMMU.
312 * - Normal memory is accessed through SMMU and ordering is
313 * ensured by client and AXI.
314 * - Ack point for Normal memory is WCAM in MC.
315 * - MMIO's can be early acked and AXI ensures dev memory ordering,
316 * Client ensures read/write direction change ordering.
317 * - See Bug 200312466 for more details.
318 *
319 * CGID_TAG_ADR is only present from T186 A02. As this code is common
320 * between A01 and A02, tegra_memctrl_set_overrides() programs
321 * CGID_TAG_ADR for the necessary clients on A02.
322 */
323 mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
324 mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
325 mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
326 mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
327 mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
328 mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
329 mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
330 mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
331 mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
332 mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
333 mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
334 mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
335 mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
336 mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
337 mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
338 /* See bug 200131110 comment #35*/
339 mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
340 mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
341 mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
342 mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
343 mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
344 mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
345 mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
346 mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
347 mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
348 mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
349 mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
350 mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
351 mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
352 mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
353 mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
354 mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
355 mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
356 mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
357 mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
358 /* See bug 200131110 comment #35*/
359 mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
360 mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
361 mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
362 mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
363 mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
364 mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
365 mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
366 mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
367 mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
368 mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
369 mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
370 mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
371 mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
372 mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
373 mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
374 mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
375 mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
376 mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
377 mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
378 mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
379 mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
380 mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
381 mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
382 mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
383 mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
384 mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
385 /* See bug 200131110 comment #35 */
386 mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
387 mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
388 mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
389 mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
390 mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
391 mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
392 mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
393 mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
394 mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
395 mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
396 /*
397 * See bug 200131110 comment #35 - there are no normal requests
398 * and AWID for SO/DEV requests is hardcoded in RTL for a
399 * particular PCIE controller
400 */
401 mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT);
402 mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
403
404 /*
405 * At this point, ordering can occur at ROC. So, remove PCFIFO's
406 * control over ordering requests.
407 *
408 * Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
409 * boot and strongly ordered MSS clients
410 */
411 val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530412 mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530413 mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
414 mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
415 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
416
417 val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
418 mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
419 mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW);
420 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val);
421
422 val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
423 mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB);
424 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val);
425
426 val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
427 mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
428 mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
429 mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
430 mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
431 mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
432 mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
433 mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
434 /* EQOSW is the only client that has PCFIFO order enabled. */
435 val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
436 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val);
437
438 val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
439 mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW);
440 tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val);
441
442 /*
443 * Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS
444 * clients to allow memory traffic from all clients to start passing
445 * through ROC
446 */
447 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
448 assert(val == wdata_0);
449
450 wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
451 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
452
453 val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
454 assert(val == wdata_1);
455
456 wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
457 tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
458
459#endif
460}
461
462static void tegra186_memctrl_set_overrides(void)
463{
464 const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
465 const mc_txn_override_cfg_t *mc_txn_override_cfgs;
466 uint32_t num_txn_override_cfgs;
467 uint32_t i, val;
468
469 /* Get the settings from the platform */
470 assert(plat_mc_settings != NULL);
471 mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
472 num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
473
474 /*
475 * Set the MC_TXN_OVERRIDE registers for write clients.
476 */
477 if ((tegra_chipid_is_t186()) &&
478 (!tegra_platform_is_silicon() ||
479 (tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) {
480
481 /*
482 * GPU and NVENC settings for Tegra186 simulation and
483 * Silicon rev. A01
484 */
485 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
486 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
487 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
488 val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
489
490 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
491 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
492 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
493 val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
494
495 val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
496 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
497 tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
498 val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
499
500 } else {
501
502 /*
503 * Settings for Tegra186 silicon rev. A02 and onwards.
504 */
505 for (i = 0; i < num_txn_override_cfgs; i++) {
506 val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
507 val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
508 tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
509 val | mc_txn_override_cfgs[i].cgid_tag);
510 }
511 }
512}
513
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530514/*******************************************************************************
515 * Struct to hold the memory controller settings
516 ******************************************************************************/
517static tegra_mc_settings_t tegra186_mc_settings = {
518 .streamid_override_cfg = tegra186_streamid_override_regs,
Anthony Zhou0e07e452017-07-26 17:16:54 +0800519 .num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_override_regs),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530520 .streamid_security_cfg = tegra186_streamid_sec_cfgs,
Anthony Zhou0e07e452017-07-26 17:16:54 +0800521 .num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs),
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530522 .txn_override_cfg = tegra186_txn_override_cfgs,
Puneet Saxenacf8c0e22017-08-04 17:19:55 +0530523 .num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs),
524 .reconfig_mss_clients = tegra186_memctrl_reconfig_mss_clients,
525 .set_txn_overrides = tegra186_memctrl_set_overrides,
Pritesh Raithatha9eb5db52017-01-02 19:42:31 +0530526};
527
528/*******************************************************************************
529 * Handler to return the pointer to the memory controller's settings struct
530 ******************************************************************************/
531tegra_mc_settings_t *tegra_get_mc_settings(void)
532{
533 return &tegra186_mc_settings;
534}
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700535
536/*******************************************************************************
537 * Handler to program the scratch registers with TZDRAM settings for the
538 * resume firmware
539 ******************************************************************************/
540void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
541{
542 uint32_t val;
543
Steven Kaoa457f2e2017-11-14 18:52:05 +0800544 /*
545 * Setup the Memory controller to allow only secure accesses to
546 * the TZDRAM carveout
547 */
548 INFO("Configuring TrustZone DRAM Memory Carveout\n");
549
550 tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
551 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
552 tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700553
554 /*
555 * When TZ encryption is enabled, we need to setup TZDRAM
556 * before CPU accesses TZ Carveout, else CPU will fetch
557 * non-decrypted data. So save TZDRAM setting for SC7 resume
558 * FW to restore.
559 *
560 * Scratch registers map:
561 * RSV55_0 = CFG1[12:0] | CFG0[31:20]
562 * RSV55_1 = CFG3[1:0]
563 */
564 val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK;
565 val |= tegra_mc_read_32(MC_SECURITY_CFG0_0) & MC_SECURITY_BOM_MASK;
Steven Kao186485e2017-10-23 18:22:09 +0800566 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_LO, val);
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700567
568 val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK;
Steven Kao186485e2017-10-23 18:22:09 +0800569 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_TZDRAM_ADDR_HI, val);
Steven Kaoa457f2e2017-11-14 18:52:05 +0800570
571 /*
572 * MCE propagates the security configuration values across the
573 * CCPLEX.
574 */
575 (void)mce_update_gsc_tzdram();
Varun Wadekarf3cd5092017-10-30 14:35:17 -0700576}