blob: cb1bc1862dd5b91ae1d0269006e6590fdfa23eb1 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handley0cdebbd2015-03-30 17:15:16 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Juan Castilloa08a5e72015-05-19 11:54:12 +010034#include <auth_mod.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010035#include <bl1.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010036#include <bl_common.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010037#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010038#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010039#include <platform_def.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010040#include <smcc_helpers.h>
Soby Mathewc53ac5e2016-07-20 14:38:36 +010041#include <utils.h>
Dan Handleybcd60ba2014-04-17 18:53:42 +010042#include "bl1_private.h"
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010043#include <uuid.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010045/* BL1 Service UUID */
46DEFINE_SVC_UUID(bl1_svc_uid,
47 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75,
48 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a);
49
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010050
Yatharth Kochara65be2f2015-10-09 18:06:13 +010051static void bl1_load_bl2(void);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010052
Sandrine Bailleux467d0572014-06-24 14:02:34 +010053/*******************************************************************************
54 * The next function has a weak definition. Platform specific code can override
55 * it if it wishes to.
56 ******************************************************************************/
57#pragma weak bl1_init_bl2_mem_layout
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010058
59/*******************************************************************************
Sandrine Bailleux467d0572014-06-24 14:02:34 +010060 * Function that takes a memory layout into which BL2 has been loaded and
61 * populates a new memory layout for BL2 that ensures that BL1's data sections
62 * resident in secure RAM are not visible to BL2.
63 ******************************************************************************/
64void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
65 meminfo_t *bl2_mem_layout)
66{
67 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
68
69 assert(bl1_mem_layout != NULL);
70 assert(bl2_mem_layout != NULL);
71
72 /* Check that BL1's memory is lying outside of the free memory */
73 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
Yatharth Kochara65be2f2015-10-09 18:06:13 +010074 (BL1_RAM_BASE >= bl1_mem_layout->free_base +
75 bl1_mem_layout->free_size));
Sandrine Bailleux467d0572014-06-24 14:02:34 +010076
77 /* Remove BL1 RW data from the scope of memory visible to BL2 */
78 *bl2_mem_layout = *bl1_mem_layout;
79 reserve_mem(&bl2_mem_layout->total_base,
80 &bl2_mem_layout->total_size,
81 BL1_RAM_BASE,
82 bl1_size);
83
84 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
85}
86
87/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +010088 * Function to perform late architectural and platform specific initialization.
Yatharth Kochara65be2f2015-10-09 18:06:13 +010089 * It also queries the platform to load and run next BL image. Only called
90 * by the primary cpu after a cold boot.
91 ******************************************************************************/
Achin Gupta4f6ad662013-10-25 09:08:21 +010092void bl1_main(void)
93{
Yatharth Kochara65be2f2015-10-09 18:06:13 +010094 unsigned int image_id;
95
Dan Handley91b624e2014-07-29 17:14:00 +010096 /* Announce our arrival */
97 NOTICE(FIRMWARE_WELCOME_STR);
98 NOTICE("BL1: %s\n", version_string);
99 NOTICE("BL1: %s\n", build_message);
100
101 INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT);
102
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103
Dan Handley0cdebbd2015-03-30 17:15:16 +0100104#if DEBUG
105 unsigned long val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106 /*
107 * Ensure that MMU/Caches and coherency are turned on
108 */
Dan Handley0cdebbd2015-03-30 17:15:16 +0100109 val = read_sctlr_el3();
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100110 assert(val & SCTLR_M_BIT);
111 assert(val & SCTLR_C_BIT);
112 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100113 /*
114 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
115 * provided platform value
116 */
117 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
118 /*
119 * If CWG is zero, then no CWG information is available but we can
120 * at least check the platform value is less than the architectural
121 * maximum.
122 */
123 if (val != 0)
124 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
125 else
126 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
127#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128
129 /* Perform remaining generic architectural setup from EL3 */
130 bl1_arch_setup();
131
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100132#if TRUSTED_BOARD_BOOT
133 /* Initialize authentication module */
134 auth_mod_init();
135#endif /* TRUSTED_BOARD_BOOT */
136
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137 /* Perform platform setup in BL1. */
138 bl1_platform_setup();
139
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100140 /* Get the image id of next image to load and run. */
141 image_id = bl1_plat_get_next_image_id();
142
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100143 /*
144 * We currently interpret any image id other than
145 * BL2_IMAGE_ID as the start of firmware update.
146 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100147 if (image_id == BL2_IMAGE_ID)
148 bl1_load_bl2();
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100149 else
150 NOTICE("BL1-FWU: *******FWU Process Started*******\n");
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100151
152 bl1_prepare_next_image(image_id);
153}
154
155/*******************************************************************************
156 * This function locates and loads the BL2 raw binary image in the trusted SRAM.
157 * Called by the primary cpu after a cold boot.
158 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
159 * loader etc.
160 ******************************************************************************/
161void bl1_load_bl2(void)
162{
163 image_desc_t *image_desc;
164 image_info_t *image_info;
165 entry_point_info_t *ep_info;
166 meminfo_t *bl1_tzram_layout;
167 meminfo_t *bl2_tzram_layout;
168 int err;
169
170 /* Get the image descriptor */
171 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
172 assert(image_desc);
173
174 /* Get the image info */
175 image_info = &image_desc->image_info;
176
177 /* Get the entry point info */
178 ep_info = &image_desc->ep_info;
Vikram Kanigirida567432014-04-15 18:08:08 +0100179
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100180 /* Find out how much free trusted ram remains after BL1 load */
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +0000181 bl1_tzram_layout = bl1_plat_sec_mem_layout();
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100182
Juan Castillo3a66aca2015-04-13 17:36:19 +0100183 INFO("BL1: Loading BL2\n");
184
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100185 /* Load the BL2 image */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100186 err = load_auth_image(bl1_tzram_layout,
Juan Castillo3a66aca2015-04-13 17:36:19 +0100187 BL2_IMAGE_ID,
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100188 image_info->image_base,
189 image_info,
190 ep_info);
Juan Castilloa08a5e72015-05-19 11:54:12 +0100191
Vikram Kanigirida567432014-04-15 18:08:08 +0100192 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100193 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100194 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100195 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000196
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197 /*
198 * Create a new layout of memory for BL2 as seen by BL1 i.e.
199 * tell it the amount of total and free memory available.
200 * This layout is created at the first free address visible
201 * to BL2. BL2 will read the memory layout before using its
202 * memory for other purposes.
203 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100204 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100205 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100206
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100207 ep_info->args.arg1 = (unsigned long)bl2_tzram_layout;
208 NOTICE("BL1: Booting BL2\n");
209 VERBOSE("BL1: BL2 memory layout address = 0x%llx\n",
210 (unsigned long long) bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100211}
212
213/*******************************************************************************
Sandrine Bailleux33c95cc2015-10-27 15:52:33 +0000214 * Function called just before handing over to BL31 to inform the user about
215 * the boot progress. In debug mode, also print details about the BL31 image's
216 * execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100217 ******************************************************************************/
Sandrine Bailleux33c95cc2015-10-27 15:52:33 +0000218void bl1_print_bl31_ep_info(const entry_point_info_t *bl31_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100219{
Juan Castillo7d199412015-12-14 09:35:25 +0000220 NOTICE("BL1: Booting BL31\n");
Sandrine Bailleuxb2e224c2015-09-28 17:03:06 +0100221 print_entry_point_info(bl31_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222}
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000223
224#if SPIN_ON_BL1_EXIT
225void print_debug_loop_message(void)
226{
227 NOTICE("BL1: Debug loop, spinning forever\n");
228 NOTICE("BL1: Please connect the debugger to continue\n");
229}
230#endif
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100231
232/*******************************************************************************
233 * Top level handler for servicing BL1 SMCs.
234 ******************************************************************************/
235register_t bl1_smc_handler(unsigned int smc_fid,
236 register_t x1,
237 register_t x2,
238 register_t x3,
239 register_t x4,
240 void *cookie,
241 void *handle,
242 unsigned int flags)
243{
244
245#if TRUSTED_BOARD_BOOT
246 /*
247 * Dispatch FWU calls to FWU SMC handler and return its return
248 * value
249 */
250 if (is_fwu_fid(smc_fid)) {
251 return bl1_fwu_smc_handler(smc_fid, x1, x2, x3, x4, cookie,
252 handle, flags);
253 }
254#endif
255
256 switch (smc_fid) {
257 case BL1_SMC_CALL_COUNT:
258 SMC_RET1(handle, BL1_NUM_SMC_CALLS);
259
260 case BL1_SMC_UID:
261 SMC_UUID_RET(handle, bl1_svc_uid);
262
263 case BL1_SMC_VERSION:
264 SMC_RET1(handle, BL1_SMC_MAJOR_VER | BL1_SMC_MINOR_VER);
265
266 default:
267 break;
268 }
269
270 WARN("Unimplemented BL1 SMC Call: 0x%x \n", smc_fid);
271 SMC_RET1(handle, SMC_UNK);
272}