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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handley0cdebbd2015-03-30 17:15:16 +01002 * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
Dan Handley2bd4ef22014-04-09 13:14:54 +010031#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <arch_helpers.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <assert.h>
Juan Castilloa08a5e72015-05-19 11:54:12 +010034#include <auth_mod.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010035#include <bl_common.h>
Vikram Kanigirida567432014-04-15 18:08:08 +010036#include <debug.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010037#include <platform.h>
Dan Handleyed6ff952014-05-14 17:44:19 +010038#include <platform_def.h>
Dan Handleybcd60ba2014-04-17 18:53:42 +010039#include "bl1_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
41/*******************************************************************************
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010042 * Runs BL2 from the given entry point. It results in dropping the
43 * exception level
44 ******************************************************************************/
Vikram Kanigirida567432014-04-15 18:08:08 +010045static void __dead2 bl1_run_bl2(entry_point_info_t *bl2_ep)
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010046{
Vikram Kanigiriceb0d0f2015-07-23 11:16:28 +010047 /* Check bl2 security state is expected as secure */
48 assert(GET_SECURITY_STATE(bl2_ep->h.attr) == SECURE);
49 /* Check NS Bit is also set as secure */
50 assert(!(read_scr_el3() & SCR_NS_BIT));
51
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010052 bl1_arch_next_el_setup();
53
54 /* Tell next EL what we want done */
55 bl2_ep->args.arg0 = RUN_IMAGE;
56
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010057 write_spsr_el3(bl2_ep->spsr);
Vikram Kanigirida567432014-04-15 18:08:08 +010058 write_elr_el3(bl2_ep->pc);
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010059
Sandrine Bailleuxb2e224c2015-09-28 17:03:06 +010060 NOTICE("BL1: Booting BL2\n");
61 print_entry_point_info(bl2_ep);
62
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010063 eret(bl2_ep->args.arg0,
64 bl2_ep->args.arg1,
65 bl2_ep->args.arg2,
66 bl2_ep->args.arg3,
67 bl2_ep->args.arg4,
68 bl2_ep->args.arg5,
69 bl2_ep->args.arg6,
70 bl2_ep->args.arg7);
71}
72
Sandrine Bailleux467d0572014-06-24 14:02:34 +010073/*******************************************************************************
74 * The next function has a weak definition. Platform specific code can override
75 * it if it wishes to.
76 ******************************************************************************/
77#pragma weak bl1_init_bl2_mem_layout
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010078
79/*******************************************************************************
Sandrine Bailleux467d0572014-06-24 14:02:34 +010080 * Function that takes a memory layout into which BL2 has been loaded and
81 * populates a new memory layout for BL2 that ensures that BL1's data sections
82 * resident in secure RAM are not visible to BL2.
83 ******************************************************************************/
84void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
85 meminfo_t *bl2_mem_layout)
86{
87 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
88
89 assert(bl1_mem_layout != NULL);
90 assert(bl2_mem_layout != NULL);
91
92 /* Check that BL1's memory is lying outside of the free memory */
93 assert((BL1_RAM_LIMIT <= bl1_mem_layout->free_base) ||
94 (BL1_RAM_BASE >= bl1_mem_layout->free_base + bl1_mem_layout->free_size));
95
96 /* Remove BL1 RW data from the scope of memory visible to BL2 */
97 *bl2_mem_layout = *bl1_mem_layout;
98 reserve_mem(&bl2_mem_layout->total_base,
99 &bl2_mem_layout->total_size,
100 BL1_RAM_BASE,
101 bl1_size);
102
103 flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
104}
105
106/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100107 * Function to perform late architectural and platform specific initialization.
108 * It also locates and loads the BL2 raw binary image in the trusted DRAM. Only
109 * called by the primary cpu after a cold boot.
110 * TODO: Add support for alternative image load mechanism e.g using virtio/elf
111 * loader etc.
112 ******************************************************************************/
113void bl1_main(void)
114{
Dan Handley91b624e2014-07-29 17:14:00 +0100115 /* Announce our arrival */
116 NOTICE(FIRMWARE_WELCOME_STR);
117 NOTICE("BL1: %s\n", version_string);
118 NOTICE("BL1: %s\n", build_message);
119
120 INFO("BL1: RAM 0x%lx - 0x%lx\n", BL1_RAM_BASE, BL1_RAM_LIMIT);
121
Vikram Kanigirida567432014-04-15 18:08:08 +0100122 image_info_t bl2_image_info = { {0} };
123 entry_point_info_t bl2_ep = { {0} };
Dan Handleye2712bc2014-04-10 15:37:22 +0100124 meminfo_t *bl1_tzram_layout;
125 meminfo_t *bl2_tzram_layout = 0x0;
Vikram Kanigirida567432014-04-15 18:08:08 +0100126 int err;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100127
Dan Handley0cdebbd2015-03-30 17:15:16 +0100128#if DEBUG
129 unsigned long val;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100130 /*
131 * Ensure that MMU/Caches and coherency are turned on
132 */
Dan Handley0cdebbd2015-03-30 17:15:16 +0100133 val = read_sctlr_el3();
Andrew Thoelke5e287b52015-06-11 14:12:14 +0100134 assert(val & SCTLR_M_BIT);
135 assert(val & SCTLR_C_BIT);
136 assert(val & SCTLR_I_BIT);
Dan Handley0cdebbd2015-03-30 17:15:16 +0100137 /*
138 * Check that Cache Writeback Granule (CWG) in CTR_EL0 matches the
139 * provided platform value
140 */
141 val = (read_ctr_el0() >> CTR_CWG_SHIFT) & CTR_CWG_MASK;
142 /*
143 * If CWG is zero, then no CWG information is available but we can
144 * at least check the platform value is less than the architectural
145 * maximum.
146 */
147 if (val != 0)
148 assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
149 else
150 assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
151#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100152
153 /* Perform remaining generic architectural setup from EL3 */
154 bl1_arch_setup();
155
156 /* Perform platform setup in BL1. */
157 bl1_platform_setup();
158
Vikram Kanigirida567432014-04-15 18:08:08 +0100159 SET_PARAM_HEAD(&bl2_image_info, PARAM_IMAGE_BINARY, VERSION_1, 0);
160 SET_PARAM_HEAD(&bl2_ep, PARAM_EP, VERSION_1, 0);
161
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100162 /* Find out how much free trusted ram remains after BL1 load */
Sandrine Bailleuxee12f6f2013-11-28 14:55:58 +0000163 bl1_tzram_layout = bl1_plat_sec_mem_layout();
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100164
Juan Castillo3a66aca2015-04-13 17:36:19 +0100165 INFO("BL1: Loading BL2\n");
166
Juan Castillod227d8b2015-01-07 13:49:59 +0000167#if TRUSTED_BOARD_BOOT
168 /* Initialize authentication module */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100169 auth_mod_init();
Juan Castillod227d8b2015-01-07 13:49:59 +0000170#endif /* TRUSTED_BOARD_BOOT */
171
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100172 /* Load the BL2 image */
Juan Castilloa08a5e72015-05-19 11:54:12 +0100173 err = load_auth_image(bl1_tzram_layout,
Juan Castillo3a66aca2015-04-13 17:36:19 +0100174 BL2_IMAGE_ID,
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100175 BL2_BASE,
176 &bl2_image_info,
177 &bl2_ep);
Juan Castilloa08a5e72015-05-19 11:54:12 +0100178
Vikram Kanigirida567432014-04-15 18:08:08 +0100179 if (err) {
Dan Handley91b624e2014-07-29 17:14:00 +0100180 ERROR("Failed to load BL2 firmware.\n");
Juan Castillo26ae5832015-09-25 15:41:14 +0100181 plat_error_handler(err);
Vikram Kanigirida567432014-04-15 18:08:08 +0100182 }
Juan Castillod227d8b2015-01-07 13:49:59 +0000183
Achin Gupta4f6ad662013-10-25 09:08:21 +0100184 /*
185 * Create a new layout of memory for BL2 as seen by BL1 i.e.
186 * tell it the amount of total and free memory available.
187 * This layout is created at the first free address visible
188 * to BL2. BL2 will read the memory layout before using its
189 * memory for other purposes.
190 */
Dan Handleye2712bc2014-04-10 15:37:22 +0100191 bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base;
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100192 bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193
Vikram Kanigirida567432014-04-15 18:08:08 +0100194 bl1_plat_set_bl2_ep_info(&bl2_image_info, &bl2_ep);
195 bl2_ep.args.arg1 = (unsigned long)bl2_tzram_layout;
Vikram Kanigirida567432014-04-15 18:08:08 +0100196 bl1_run_bl2(&bl2_ep);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100197
Achin Gupta4f6ad662013-10-25 09:08:21 +0100198 return;
199}
200
201/*******************************************************************************
Sandrine Bailleux33c95cc2015-10-27 15:52:33 +0000202 * Function called just before handing over to BL31 to inform the user about
203 * the boot progress. In debug mode, also print details about the BL31 image's
204 * execution context.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100205 ******************************************************************************/
Sandrine Bailleux33c95cc2015-10-27 15:52:33 +0000206void bl1_print_bl31_ep_info(const entry_point_info_t *bl31_ep_info)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100207{
Dan Handley91b624e2014-07-29 17:14:00 +0100208 NOTICE("BL1: Booting BL3-1\n");
Sandrine Bailleuxb2e224c2015-09-28 17:03:06 +0100209 print_entry_point_info(bl31_ep_info);
Achin Gupta4f6ad662013-10-25 09:08:21 +0100210}